Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
18-104 Freescale Semiconductor
synchronous. The SDS signal is not generated by FCK, rather both are generated by the system clock, so
that it is not guaranteed that FCK edges precede SDS edges. While SDS is negated, the slave continuously
drives its msb bit on every positive edge of FCK until it detects an asserted SDS on the immediately next
FCK negative edge. Refer to
Figure 18-58 for three situations showing how the slave should behave
according to when SDS is asserted.
NOTE
On the master, the FCK is not used as a clock. Although, the eQADC SSI
behavior is described in terms of the FCK positive and negative edges, all
eQADC SSI related signals (SDI, SDS, SDO, and FCK) are synchronized
by the system clock on the master side. There are no restrictions regarding
the use of the FCK as a clock on the slave device.
18.4.8.1.1 Abort Feature
The master indicates it is aborting the current transfer by negating SDS before the whole data frame has
being shifted out, that is the 26th bit of data being transferred has not being shifted out. The eQADC
ignores the incompletely received message. The eQADC re-sends the aborted message whenever the
corresponding CFIFO becomes again the highest priority CFIFO with commands bound for an external
command buffer that is not full. Refer to
Section 18.4.3.2, “CFIFO Prioritization and Command Transfer ,”
for more information on aborts and CFIFO priority.
18.4.8.2 Baud Clock Generation
As shown in Figure 18-55 , the baud clock generator divides the system clock to produce the baud clock.
The EQADC_SSICR[BR] field (see Section 18.3.2.12, “eQADC SSI Control Register
(EQADC_SSICR) ”) selects the system clock divide factor as in Table 18-21 .
1
1. Maximum FCK frequency is highly dependable on track delays, master pad delays, and slave pad delays.
BaudClockFrequency
SystemClockFrequency MHz
( )
SystemClockDivideFactor
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