External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor
12-27
The address transfer phase specifies the address for the transaction and the transfer attributes that describe
the transaction. The signals related to the address transfer phase are TS, ADDR, CS[0:3], RD_WR, and
BDIP. The address and its related signals (with the exception of TS, BDIP) are driven on the bus with the
assertion of the TS signal, and kept valid until the bus master receives TA asserted (the EBI holds them
one cycle beyond TA for writes and external TA accesses). For writes with internal TA, RD_WR is not
held one cycle past TA.
The data transfer phase performs the transfer of data, from master to slave (in write cycles) or from slave
to master (on read cycles), if any is to be transferred. The data phase may transfer a single beat of data (1-4
bytes) for non-burst operations or a 2-beat (special EBI_MCR[DBM] = 1 case only), 4-beat, 8-beat, or
16-beat burst of data (2 or 4 bytes per beat depending on port size) when burst is enabled. On a write cycle,
the master must not drive write data until after the address transfer phase is complete. This is to avoid
electrical contentions when switching between drivers. The master must start driving write data one cycle
after the address transfer cycle. The master can stop driving the data bus as soon as it samples the TA line
asserted on the rising edge of CLKOUT. To facilitate asynchronous write support, the EBI keeps driving
valid write data on the data bus until 1 clock after the rising edge where RD_WR (and WE for chip select
accesses) are negated.
Refer to
for an example of write timing. On a read cycle, the master accepts the data bus
contents as valid on the rising edge of the CLKOUT in which the TA signal is sampled asserted. Refer to
for an example of read timing.
The termination phase is where the cycle is terminated by the assertion of either TA (normal termination)
or TEA (termination with error). Termination is discussed in detail in
Section 12.4.2.9, “Termination
.”
12.4.2.4
Single-Beat Transfer
The flow and timing diagrams in this section assume that the EBI is configured in single master mode.
Therefore, arbitration is not needed and is not shown in these diagrams. Refer to
Operation in External Master Mode
,” to read how the flow and timing diagrams change for external master
mode.
12.4.2.4.1
Single-Beat Read Flow
The handshakes for a single beat read cycle are illustrated in the following flow and timing diagrams.
Summary of Contents for MPC5565
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Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...
