Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 17-39
17.4.6.1 Channel Registers Layout
One contiguous area is used to map all channel registers of each eTPU engine as shown in Table 17-24 .
There are 64 structures defined, one for each available channel in the eTPU System (32 for each engine).
The base address for the structure presented can be calculated by using the following equation:
where:
17.4.6.2 eTPU Channel n Configuration Register (ETPU_C n CR)
The ETPU_C n CR is a collection of the configuration bits related to an individual channel. Some of these
bits are mirrored from the global channel registers.
Table 17-24. eTPU Channel Register Map
Address Registers Structure
Base + 0x0000_0400 eTPU A channel 0 register structure
Base + 0x0000_0410 eTPU A channel 1 register structure
Base + 0x0000_0420 eTPU A channel 2 register structure
Base + 0x0000_0430–
Base + 0x0000_05D0
.
.
.
Base + 0x0000_05E0 eTPU A channel 30 register structure
Base + 0x0000_05F0 eTPU A channel 31 register structure
Base + 0x0000_0600–
Base + 0x0000_07FF
Reserved
Address: Channel_Registe 0x0000 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
CIE DTRE CPR
0 0
ETPD ETCS
0 0 0
CFS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ODIS OPOL
0 0 0
CPBA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-22. ETPU Channel n Configuration Register (ETPU_C n CR
)
Channel_Register_Structure_Base_Address ETPU_Engine_Channel_Base channel_number 0x0000_0010
×
( )
+ =
ETPU_Engine_Channel_Base ETPU_Base 0x0000_0400 = ETPU A + =