Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Serial Communication Interface (eSCI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 20-25
20.4.4.5 Fast Bit Error Detection in LIN Mode
Fast bit error detection has been designed to allow flagging of LIN bit errors while they occur, rather than
flagging them after a byte transmission has completed. To use this feature, it is assumed a physical
interface connects to the LIN bus as shown in
Figure 20-14 .
Figure 20-14. Fast Bit Error Detection on a LIN Bus
If fast bit error detection is enabled (FBR = 1), the eSCI compares the transmitted and the received data
stream when the transmitter is active (not idle). After a mismatch between the transmitted data and the
received data is detected the following actions are performed:
• The LIN frame is aborted (provided LDBG=0).
• The bit error flag BERR is set.
• If SBSTP is 0, the remainder of the byte is transmitted normally.
• If SBSTP is 1, the remaining bits in the byte after the error bit are transmitted as 1s (idle).
To adjust to different bus loads the sample point at which the incoming bit is compared to the one which
was transmitted can be selected with the BESM13 bit (refer to
Figure 20-15 ). If set, the comparison is
performed at RT clock 13, otherwise at RT clock 9 (refer to Section 20.4.5.3, “Data Sampling .”).
Figure 20-15. Fast Bit Error Detection Timing Diagram
Bus Clock
Compare
Bit Error
Receive Shift
Register
Transmit Shift
Register
Sample Point
LIN Bus
RxD Pin
TxD Pin
Synchronizer Stage
LIN Physical Interface
Clock
BESM13 = 0 BESM13 = 1
1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 RT Clock
Count
TX Output
Shift Reg
RX Input
Shift Reg
Compare
Sample
Points