Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-11
17
MDIS
Module disable. Allows the clock to stop to the non-memory mapped logic in the DSPI, effectively putting the
DSPI in a software controlled power-saving state. Refer to
Section 19.4.10, “Power Saving Features for more
information.” The reset value of the MDIS bit is parameterized, with a default reset value of 0.
0 Enable DSPI clocks
1 Allow external logic to disable DSPI clocks
18
DIS_TXF
Disable transmit FIFO. Enables and disables the TX FIFO. When the TX FIFO is disabled, the transmit part
of the DSPI operates as a simplified double-buffered SPI. Refer to
Section 19.4.3.3, “FIFO Disable Operation
for details.”
0 TX FIFO is enabled
1 TX FIFO is disabled
19
DIS_RXF
Disable receive FIFO. Enables and disables the RX FIFO. When the RX FIFO is disabled, the receive part of
the DSPI operates as a simplified double-buffered SPI. Refer to
Section 19.4.3.3, “FIFO Disable Operation
for details.”
0 RX FIFO is enabled
1 RX FIFO is disabled
20
CLR_TXF
Clear TX FIFO. Flushes the TX FIFO. Write a 1 to the CLR_TXF bit to clear the TX FIFO counter. The
CLR_TXF bit is always read as zero.
0 Do not clear the TX FIFO counter
1 Clear the TX FIFO counter
21
CLR_RXF
Clear RX FIFO. Flushes the RX FIFO. Write a 1 to the CLR_RXF bit to clear the RX counter. The CLR_RXF
bit is always read as zero.
0 Do not clear the RX FIFO counter
1 Clear the RX FIFO counter
22–23
SMPL_
PT
[0:1]
Sample point. Allows the host software to select when the DSPI master samples SIN in modified transfer
format.
Figure 19-34 shows where the master can sample the SIN pin. The following table lists the delayed
sample points.
24–30 Reserved.
31
HALT
Halt. Provides a mechanism for software to start and stop DSPI transfers. Refer to Section 19.4.2, “Start and
Stop of DSPI Transfers ,” for details on the operation of this bit.
0 Start transfers
1 Stop transfers
Table 19-3. DSPI x _MCR Field Descriptions (continued)
Field Description
SMPL_PT
Number of system clock cycles between
odd-numbered edge of SCK x and sampling of SIN x .
00 0
01 1
10 2
11 Invalid value