Nexus
MPC5565 Microcontroller Reference Manual, Rev. 1.0
24-50
Freescale Semiconductor
24.11.12.1.1
e200z
6
Indirect Branch Message Instructions (Power Architecture Book E)
shows the types of instructions and events which cause indirect branch messages or branch
history messages to be encoded.
24.11.12.1.2
e200z6 Direct Branch Message Instructions (Power Architecture Book E)
shows the types of instructions which will cause direct branch messages or will toggle a bit in
the instruction history buffer to be messaged out in a resource full message or branch history message.
24.11.12.1.3 BTM Using Branch History Messages
Traditional BTM messaging can accurately track the number of sequential instructions between branches,
but cannot accurately indicate which instructions were conditionally executed, and which were not.
Branch history messaging solves this problem by providing a predicated instruction history field in each
indirect branch message. Each bit in the history represents a predicated instruction or direct branch. A
value of one (1) indicates the conditional instruction was executed or the direct branch was taken. A value
of zero (0) indicates the conditional instruction was not executed or the direct branch was not taken.
Certain instructions (
evsel
) generate a pair of predicate bits which are both reported as consecutive bits in
the history field.
Branch history messages solve predicated instruction tracking and save bandwidth since only indirect
branches cause messages to be queued.
24.11.12.1.4 BTM Using Traditional Program Trace Messages
Based on the PTM bit in the DC register (DC[PTM]), program tracing can utilize either branch history
messages (DC[PTM] = 1) or traditional direct/indirect branch messages (DC[PTM] = 0).
Branch history will save bandwidth and keep consistency between methods of program trace, yet may lose
temporal order between BTM messages and other types of messages. Since direct branches are not
messaged, but are instead included in the history field of the indirect branch history message, other types
of messages may enter the FIFO between branch history messages. The development tool cannot
determine the ordering of “events” that occurred with respect to direct branches simply by the order in
which messages are sent out.
Table 24-34. Indirect Branch Message Sources
Source of Indirect Branch Message
Instructions
Taken branch relative to a register value
bcctr, bcctrl, bclr, bclrl
System call / trap exceptions taken
sc, tw, twi
Return from interrupts / exceptions
rfi, rfci, rfdi
Table 24-35. Direct Branch Message Sources
Source of Direct Branch Message
Instructions
Taken direct branch instructions
b, ba, bl, bla, bc, bca, bcl, bcla
Instruction synchronize
isync
Summary of Contents for MPC5565
Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...
Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...
Page 35: ...MPC5565 Reference Manual Rev 1 0 16 Freescale Semiconductor...
Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...