Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
9-30 Freescale Semiconductor
9.3.2 eDMA Basic Data Flow
The basic flow of a data transfer can be partitioned into three segments. As shown in Figure 9-19 , the first
segment involves the channel service request. In the diagram, this example uses the assertion of the eDMA
peripheral request signal to request service for channel
n . Channel service request via software and the
TCDn.START bit follows the same basic flow as an eDMA peripheral request. The eDMA peripheral
request input signal is registered internally and then routed to through the eDMA engine, first through the
control module, then into the program model/channel arbitration module. In the next cycle, the channel
arbitration is performed, either using the fixed-priority or round-robin algorithm. After the arbitration is
complete, the activated channel number is sent through the address path and converted into the required
address to access the TCD local memory. Next, the TCD memory is accessed and the required descriptor
read from the local memory and loaded into the eDMA engine address path channel{x,y} registers. The
TCD memory is organized 64-bits in width to minimize the time needed to fetch the activated channel’s
descriptor and load it into the eDMA engine address path channel{x,y} registers.
Figure 9-19. eDMA Operation, Part 1
In the second part of the basic data flow as shown in Figure 9-20 , the modules associated with the data
transfer (address path, data path and control) sequence through the required source reads and destination
writes to perform the actual data movement. The source reads are initiated and the fetched data is
temporarily stored in the data path module until it is gated onto the system bus during the destination write.
Sl
ave In
te
rface
eDMA
eDMA Peripheral Request
System Bus
Data Path
Control
Address
Program Model/
Slave Write Data
Slave Write Address
Bus Write Data
Slave Read Data
Bus Address
eDMA Engine
TCD0
TCD n -1*
eDMA Interrupt Request
Bus Read Data
Channel Arbitration
eDMA Done Handshake
Path
SRAM
Transfer Control Descriptor
(TCD)
SRAM
* n = 32 channels