Freescale Semiconductor MPC5565, Reference Manual

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Error Correction Status Module (ECSM)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 8-3
8.2.1 Register Descriptions
Attempted accesses to reserved addresses result in an error termination, while attempted writes to
read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the
programming model must match the size of the register; for example, an
n -bit register only supports n -bit
writes, etc. Attempted writes of a different size than the register width produce an error termination of the
bus cycle and no change to the targeted register.
8.2.1.1 Software Watchdog Timer Control, Service, and Interrupt Registers
(ECSM_SWTCR, ECSM_SWTSR, and ECSM_SWTIR)
These registers provide control and configuration for a software watchdog timer, and are included as part
of a standard Freescale ECSM module incorporated in the device. The e200z6 core also provides this
functionality and is the preferred method for watchdog implementation. To optimize code portability to
other members of this Power Architecture-based MPU family, use of the watchdog registers in the ECSM
is not recommended.
The values in these registers should be left in their reset state. Any change from reset values may cause an
unintentional ECSM_SWTIR_SWTIC interrupt.
8.2.1.2 ECC Registers
There are a number of program-visible registers for the sole purpose of reporting and logging of memory
failures. These registers include the following:
• ECC configuration register (ECSM_ECR)
• ECC status register (ECSM_ESR)
• ECC error generation register (EEGR)
• Flash ECC address register (ECSM_FEAR)
• Flash ECC master number register (ECSM_FEMR)
• Flash ECC attributes register (ECSM_FEAT)
• Flash ECC data register (ECSM_FEDR)
• RAM ECC address register (ECSM_REAR)
• RAM ECC master number register (ECSM_REMR)
• RAM ECC attributes register (ECSM_REAT)
• RAM ECC data register (ECSM_REDR)
The details on the ECC registers are provided in the subsequent sections.
8.2.1.3 ECC Configuration Register (ECSM_ECR)
The ECSM_ECR is an 8-bit control register for specifying whether memory errors are reported during
RAM or Flash accesses. The occurrence of a non-correctable error causes the current access to be
terminated with an error condition. In many cases, this error termination is reported directly by the
initiating bus master. The ECC reporting logic in the ECSM provides an optional error interrupt
mechanism to signal non-correctable memory errors. In addition to the interrupt generation, the ECSM