Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-29
14
TRRE
Trigger reception enable. Enables the DSPI to initiate a transfer when an external trigger signal is received. The
bit is only valid in DSI configuration. Refer to
Section 19.4.4.5, “DSI Transfer Initiation Control ,” for more
information.
0 Trigger signal reception disabled
1 Trigger signal reception enabled
15
CID
Change in data transfer enable. Enables a change in serialization data to initiate a transfer. The bit is used in
master mode in DSI and CSI configurations to control when to initiate transfers. When the CID bit is set,
serialization is initiated when the current DSI data differs from the previous DSI data shifted out. The
DSPI
x _COMPR is compared with the DSPI x _SDR or DSPI x _ASDR to detect a change in data. Refer to
Section 19.4.4.5, “DSI Transfer Initiation Control ,” for more information.
0 Change in data transfer operation disabled
1 Change in data transfer operation enabled
16
DCONT
DSI continuous peripheral chip select enable. Enables the PCS x signals to remain asserted between transfers.
The DCONT bit only affects the PCS signals in DSI master mode. Refer to Section 19.4.7.5, “Continuous
Selection Format ,” for details.
0 Return peripheral chip select signals to their inactive state after transfer is complete
1 Keep peripheral chip select signals asserted after transfer is complete
17–19
DSICTAS
[0:2]
DSI clock and transfer attributes select. The DSICTAS field selects which of the DSPI x _CTARs is used to
provide transfer attributes in DSI configuration. The DSICTAS field is used in DSI master mode. In DSI slave
mode, the DSPI
x _CTAR1 is always selected. The following table lists the DSICTAS to DSPI x _CTARs mapping.
20–23 Reserved.
24–25 Reserved, but implemented. These bits are writable, but have no effect.
26–31
DPCS x
DSI peripheral chip select n . The DPCS bits select which of the PCS x signals to assert during a DSI transfer.
The DPCS bits assert and negate the PCS x signals in DSI master mode only.
0 Negate PCS x
1 Assert PCS x
Table 19-12. DSPI x _DSICR Field Descriptions (continued)
Field Description
DSICTAS
DSI Clock and Transfer Attributes
Controlled by
000 DSPIx_CTAR0
001 DSPIx_CTAR1
010 DSPIx_CTAR2
011 DSPIx_CTAR3
100 DSPIx_CTAR4
101 DSPIx_CTAR5
110 DSPIx_CTAR6
111 DSPIx_CTAR7