Freescale Semiconductor MPC5565, Reference Manual

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MPC5565 Register Map
MPC5565 Microcontroller Reference Manual, Rev. 1.0
A-2 Freescale Semiconductor
A.2 MPC5565 Register Map
The following table shows a detailed list of the MPC5565 register map:
Table A-2. MPC5565 Detailed Register Map
Register Description Register Name
Used
Size
Address
Peripheral Bridge A (PBRIDGEA)
Chapter 5, “Peripheral Bridge (PBRIDGE_A, PBRIDGE_B) ”
0xC3F0_0000
Peripheral bridge A
master privilege control register PBRIDGEA_MPCR 32-bit Base + 0x0000
Reserved — — Base + (0x0004–0x001F)
Peripheral bridge A
peripheral access control register 0 PBRIDGEA_PACR0 32-bit Base + 0x0020
Reserved — — Base + (0x0024–0x003F)
Peripheral bridge A
off-platform peripheral access control register 0 PBRIDGEA_OPACR0 32-bit Base + 0x0040
Peripheral bridge A
off-platform peripheral access control register 1 PBRIDGEA_OPACR1 32-bit Base + 0x0044
Peripheral bridge A
off-platform peripheral access control register 2 PBRIDGEA_OPACR2 32-bit Base + 0x0048
Reserved — — Base + 0x004C–0xC3F7_FFFF
Frequency Modulated Phase-Locked Loop (FMPLL)
Chapter 11, “Frequency Modulated Phase Locked Loop and System Clocks (FMPLL) ”
0xC3F8_0000
Synthesizer control register FMPLL_SYNCR 32-bit Base + 0x0000
Synthesizer status register FMPLL_SYNSR 32-bit Base + 0x0004
Reserved — — Base + 0x0008–0xC3F8_3FFF
External Bus Interface (EBI)
Chapter 12, “External Bus Interface (EBI)
0xC3F8_4000
Module configuration register EBI_MCR 32-bit Base + 0x0000
Reserved — — Base + (0x0004–0x0007)
Transfer error status register EBI_TESR 32-bit Base + 0x0008
Bus monitor control register EBI_BMCR 32-bit Base + 0x000C
Base register bank 0 EBI_BR0 32-bit Base + 0x0010
Option register bank 0 EBI_OR0 32-bit Base + 0x0014
Base register bank 1 EBI_BR1 32-bit Base + 0x0018
Option register bank 1 EBI_OR1 32-bit Base + 0x001C
Base register bank 2 EBI_BR2 32-bit Base + 0x0020
Option register bank 2 EBI_OR2 32-bit Base + 0x0024