Freescale Semiconductor MPC5565, Reference Manual

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External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
12-14 Freescale Semiconductor
12.3.1 Register Descriptions
12.3.1.1 Writing EBI Registers While a Transaction is in Progress
Other than the exceptions below, EBI registers must not be written while a transaction to the EBI (from
internal or external master) is in progress (or within 2 CLKOUT cycles after a transaction has just
completed, to allow internal state machines to go IDLE). In such cases, the behavior is undefined.
Exceptions that can be written while an EBI transaction is in progress are the following:
• All bits in EBI_TESR
• SIZE, SIZEN fields in EBI_MCR
Refer to Section 12.5.1, “Booting from External Memory ,” for additional information.
12.3.1.2 Separate Input Clock for Registers
The EBI registers are accessed with a clock signal separate from the clock used by the rest of the EBI. In
module disable mode, the clock used by the non-register portion of the EBI is disabled to reduce power
consumption. The clock signal dedicated to the registers, however, allows access to the registers even
while the EBI is in the module disable mode. Flag bits in the EBI transfer error status register (EBI_TESR),
however, are set and cleared with the clock used by the non-register portion of the EBI. Consequently, in
module disable mode, the EBI_TESR does not have a clock signal and is therefore not writable.
12.3.1.3 EBI Module Configuration Register (EBI_MCR)
The EBI_MCR contains bits that configure various attributes associated with EBI operation.
Base (0xC3F8_4000) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0
SIZEN
SIZE
0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ACGE EXTM EARB
0 0 0 0 0 0
MDIS
0 0 0 0 0
DBM
W
Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
Figure 12-2. EBI Module Configuration Register (EBI_MCR)