Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-63
The device is designed to use the same baud rate for all transfers made while using the continuous SCK.
Switching clock polarity between frames while using continuous SCK can cause errors in the transfer.
Continuous SCK operation is not guaranteed if the DSPI is put into module disable mode.
Enabling continuous SCK disables the PCS to SCK delay and the After SCK delay. The delay after transfer
is fixed at one SCK cycle.
Figure 19-39 shows timing diagram for continuous SCK format with continuous
selection disabled.
Figure 19-39. Continuous SCK Timing Diagram (CONT= 0)
If the CONT bit in the TX FIFO entry is set or the DCONT in the DSPI x _DSICR is set, PCS remains
asserted between the transfers when the PCS signal for the next transfer is the same as for the current
transfer.
Figure 19-40 shows timing diagram for continuous SCK format with continuous selection
enabled.
Figure 19-40. Continuous SCK Timing Diagram (CONT=1)
SCK
(CPOL = 0)
PCS
SCK
(CPOL = 1)
Master SOUT
t
DT
t
DT
= 1 SCK.
Master SIN
SCK
(CPOL = 0)
PCS
SCK
(CPOL = 1)
Master SOUT
Master SIN
Transfer 1 Transfer 2