Freescale Semiconductor MPC5565, Reference Manual

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External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 12-49
12.4.2.8 Arbitration
The MPC5565 does not have arbitration pins, so multi-master operation with arbitration is not supported.
However, limited dual-MCU functionality is supported for the case of a Master/Slave system.
Refer to Section 12.5.5, “Dual-MCU Operation with Reduced Pinout MCUs .”
12.4.2.9 Termination Signals Protocol
The termination signals protocol was defined to avoid electrical contention on lines that can be driven by
various sources. To do that, a slave must not drive signals associated with the data transfer until the address
phase is completed and it recognizes the address as its own. The slave must disconnect from signals
immediately after it acknowledges the cycle and not later than the termination of the next address phase
cycle.
For EBI-mastered non-chip select accesses, the EBI requires assertion of TA from an external device to
signal that the bus cycle is complete. The EBI uses a latched version of TA (1 cycle delayed) for these
accesses to help make timing at high frequencies. This results in the EBI driving the address and control
signals 1 cycle longer than required, as seen in
Figure 12-32 . However, the DATA does not need to be held
1 cycle longer by the slave, because the EBI latches DATA every cycle during non-chip select accesses.
During these accesses, the EBI does not drive the TA signal, leaving it up to an external device (or weak
internal pullup) to drive TA.
For EBI-mastered chip select accesses, the EBI drives TA the entire cycle, asserting according to internal
wait state counters to terminate the cycle. During idle periods on the external bus, the EBI drives TA
negated as long as it is granted the bus; when it no longer owns the bus it lets go of TA. When an external
master does a transaction to internal address space, the EBI only drives TA for the cycle it asserts TA to
return data and for 1 cycle afterwards to ensure fast negation.
If no device responds by asserting TA within the programmed timeout period (BMT in EBI_BMCR) after
the EBI initiates the bus cycle, the internal bus monitor (if enabled) asserts TEA to terminate the cycle. An
external device may also drive TEA when it detects an error on an external transaction. TEA assertion
causes the cycle to terminate and the processor to enter exception processing for the error condition. To
properly control termination of a bus cycle for a bus error with external circuitry, TEA must be asserted at
the same time or before (external) TA is asserted. TEA must be negated before the second rising edge after
it was sampled asserted to avoid the detection of an error for the following bus cycle initiated. TEA is only
driven by the EBI during the cycle where the EBI is asserting TEA and the cycle immediately following
this assertion (for fast negation). During all other cycles, the EBI relies on a weak internal pullup to hold
TEA negated. This allows an external device to assert TEA when it needs to indicate an error. External
devices must follow the same protocol as the EBI, only driving TEA during the assertion cycle and 1 cycle
afterwards for negation.