Freescale Semiconductor MPC5565, Reference Manual

Page: 170 / 1153

Peripheral Bridge (PBRIDGE_A, PBRIDGE_B)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 5-9
Address: Base + 0x0040 (PBRIDGE_x_OPACR0);
Base + 0x0044 (PBRIDGE_x_OPACR1);
Base + 0x0048 (PBRIDGE_x_OPACR2);
Base + 0x004C (PBRIDGE_B_OPACR3)
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
BW0 SP0 WP0 TP0 BW1 SP1 WP1 TP1 BW2 SP2 WP2 TP2 BW3 SP3 WP3 TP3
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
BW4 SP4 WP4 TP4 BW5 SP5 WP5 TP5 BW6 SP6 WP6 TP6 BW7 SP7 WP7 TP7
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Figure 5-4. Off-platform Peripheral Access Control Registers (PBRIDGE_ x _OPACR n )
Table 5-5. PBRIDGE_ x _PACR n and PBRIDGE_ x _OPACR n
Field Descriptions
Field Description
0, 4, 8, 12, 16,
20, 24, 28
BW n
1
1
In PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0, the BW0 bit is not writeable.
Buffer writes. Determines whether write accesses to this peripheral are allowed to be buffered. Write
accesses not bufferable by default
0 Write accesses to this peripheral are not bufferable by the PBRIDGE.
1 Write accesses to this peripheral are allowed to be buffered by the PBRIDGE.
Note: In PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0, the BW0 bit is not writeable.
1, 5, 9, 13, 17,
21, 25, 29
SP n
Supervisor protect. Determines whether the peripheral requires supervisor privilege level for access.
Supervisor privilege level required by default.
0 This peripheral does not require supervisor privilege level for accesses.
1 This peripheral requires supervisor privilege level for accesses. The PBRIDGE_x_MPCR[MPLy]
control bit for the master must be set. If not, the access is terminated with an error response and no
peripheral access is initiated on the slave bus.
2, 6, 10, 14, 18,
22, 26, 30
WP n
Write protect. Determines whether the peripheral allows write accesses. Write accesses allowed by
default.
0 This peripheral allows write accesses.
1 This peripheral is write protected. If a write access is attempted, the access is terminated with an error
response and no peripheral access is initiated on the slave bus.
3, 7, 11, 15, 19,
23, 27, 31
TP n
Trusted protect. Determines whether the peripheral allows accesses from an untrusted master.
0 Accesses from an untrusted master are allowed.
1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
the access is terminated with an error response and no peripheral access is initiated on the slave bus.
Access Field 0 Access Field 1 Access Field 2 Access Field 3
Access Field 4
Access Field 5 Access Field 6 Access Field 7