Freescale Semiconductor MPC5565, Reference Manual

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MPC5565 Register Map
MPC5565 Microcontroller Reference Manual, Rev. 1.0
A-56 Freescale Semiconductor
1
The registers mapped in the ECSM module (0xFFF4_0014–0xFFF4_001F) can control and configure the software watchdog timer
in the standard Freescale ECSM block incorporated in the device. The e200z6 core also provides this functionality and is the
preferred method for watchdog implementation. To optimize code portability to other members of the MPC55XX family, use of the
watchdog registers in the ECSM is not recommended.
Table A-3. e200z6 Core SPR Numbers (Supervisor Mode)
Register Description SPR (decimal)
General Registers
XER Integer Exception Register 1
LR Link Register 8
CTR Count Register 9
GPR0–GPR31 General Purpose Registers N/A
Special Purpose Registers
SPRG0 Special Purpose Register 0 272
SPRG1 Special Purpose Register 1 273
SPRG2 Special Purpose Register 2 274
SPRG3 Special Purpose Register 3 275
SPRG4 Special Purpose Register 4 276
SPRG5 Special Purpose Register 5 277
SPRG6 Special Purpose Register 6 278
SPRG7 Special Purpose Register 7 279
USPRG0 User Special Purpose Register 256
BUCSR Branch Unit Control and Status Register 1013
Exception Handling / Control Registers
SRR0 Save and Restore Register 0 26
SRR1 Save and Restore Register 1 27
CSRR0 Critical Save and Restore Register 0 58
CSRR1 Critical Save and Restore Register 1 59
DSRR0 Debug Save and Restore Register 0 574
DSRR1 Debug Save and Restore Register 1 575
ESR Exception Syndrome Register 62
MCSR Machine Check Syndrome Register 572
DEAR Data Exception Address Register 61
IVPR Interrupt Vector Prefix Register 63
IVOR1 Interrupt Vector Offset Register 1 401
IVOR2 Interrupt Vector Offset Register 2 402