Freescale Semiconductor MPC5565, Reference Manual

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Preface
MPC5565 Microcontroller Reference Manual, Rev. 1.0
21-18 Freescale Semiconductor
21.3.3.6 Error Counter Register (CAN x _ECR)
CAN x _ECR has two 8-bit fields reflecting the value of two FlexCAN2 error counters: the transmit error
counter (TXECTR field) and receive error counter (RXECTR field) . The rules for increasing and
decreasing these counters are described in the CAN protocol and are completely implemented in the
FlexCAN2 module. Both counters are read only except in freeze mode, where they can be written by the
CPU.
Writing to the CAN x _ECR while in freeze mode is an indirect operation. The data is first written to an
auxiliary register and then an internal request/acknowledge procedure across clock domains is executed.
All this is transparent to the user, except for the fact that the data will take some time to be actually written
to the register. If desired, software can poll the register to discover when the data was actually written.
FlexCAN2 responds to any bus state as described in the protocol: transmitting, for example, an ‘error
active’ or ‘error passive’ flag, delaying its transmission start time (‘error passive’), and avoiding any
influence on the bus when in the bus off state. The following are the basic rules for FlexCAN2 bus state
transitions:
• If the value of TXECTR or RXECTR increases to be greater than or equal to 128, the FLTCONF
field in the CAN
x _ESR is updated to reflect the ‘error passive’ state.
• If the FlexCAN2 state is ‘error passive,’ and either TXECTR or RXECTR decrements to a value
less than or equal to 127 while the other already satisfies this condition, the FLTCONF field in the
CAN
x _ESR is updated to reflect the ‘error active’ state.
• If the value of TXECTR increases to be greater than 255, the FLTCONF field in the CAN x _ESR
is updated to reflect the bus off state, and an interrupt may be issued. The value of TXECTR is then
reset to zero.
• If FlexCAN2 is in the bus off state, then TXECTR is cascaded together with another internal
counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence,
TXECTR is reset to zero and counts in a manner where the internal counter counts 11 such bits and
then wraps around while incrementing the TXECTR. When TXECTR reaches the value of 128, the
FLTCONF field in CAN
x _ESR is updated to be ‘error active’ and both error counters are reset to
zero. At any instance of dominant bit following a stream of less than 11 consecutive recessive bits,
the internal counter resets itself to zero without affecting the TXECTR value.
• If during system start-up, only one node is operating, then its TXECTR increases in each message
it is trying to transmit, as a result of acknowledge errors (indicated by the ACKERR bit in
CAN
x _ESR). After the transition to the ‘error passive’ state, the TXECTR does not increment
anymore by acknowledge errors. Therefore the device never goes to the bus off state.
Table 21-11. CANx_RXIMR0–CANx_RXIMR63 Field Descriptions
Field Description
0–2 Reserved.
3–13
MI28–MI18
Standard ID mask bits. These bits are the same mask bits for the standard and extended formats.
14–31
MI17–MI0
Extended ID mask bits. These bits are used to mask comparison only in extended format.