Freescale Semiconductor MPC5565, Reference Manual

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e200z6 Core Complex
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 3-13
3.3 Functional Description
The following sections describe the functions of the e200z6 core blocks.
3.3.1 Memory Management Unit (MMU)
The memory management unit (MMU) is an implementation built on the Power Architecture embedded
category with a 32-entry fully associative translation lookaside buffer (TLB). The Power Architecture
embedded category divides the effective and real address space into pages. The page represents the
granularity of effective address translation, permission control, and memory/cache attributes. The e200z6
MMU supports the following nine page sizes: (4, 16, 64, and 256 KB, 1, 4, 16, 64, and 256 MB).
3.3.1.1 Translation Lookaside Buffer (TLB)
The TLB consists of a 32-entry, fully associative content addressable memory (CAM) array. To perform a
lookup, the CAM is searched in parallel for a matching TLB entry. The contents of this TLB entry are then
concatenated with the page offset of the original effective address. The result constitutes the physical
address of the access.
Table 3-2 shows the TLB entry bit definitions.
The TLB is accessed indirectly through several MMU assist (MAS) registers. Software can read and write
to the MMU assist registers with
mtspr (move to SPR) and mfspr (move from SPR) instructions. The
Time Base The timer external clock is not connected to a clock; Do not select the timer external clock.
Context control The CTXCR and ALTCXTCR registers are not supported.
Table 3-2. TLB Entry Bit Definitions
Field Comments
V Valid bit for entry
TS Translation address space (compared against AS bit)
TID[0:7] Translation ID (compared against PID0 or ‘0’)
EPN[0:19] Effective page number (compared against effective address)
RPN[0:19] Real page number (translated address)
SIZE[0:3] Page size = 4 KB,16 KB, 64 KB, 256 KB, 1 MB, 4 MB, 16 MB, 64 MB, 256 MB
SX, SW, SR Supervisor execute, write, and read permission bits
UX, UW, UR User execute, write, and read permission bits
WIMGE Translation attributes (Write-through required, cache-inhibited, memory coherence required, guarded, endian)
U0–U3 User bits—used by software only
IPROT Invalidation protect
VLE VLE page indicator
Table 3-1. e200z6 Features Not Supported in the Device Core (continued)
Function / Category Description