Reset
MPC5565 Microcontroller Reference Manual, Rev. 1.0
4-20
Freescale Semiconductor
4.5
Document Revision History
Table 4-11. Changes Between MPC5565RM Revisions 0.1 and 1
Changed wording throughout the chapter from “PowerPC” to “Power Architecture” to comply with branding requirements.
Changed all addresses to the standard format,
• From: 0x00_0000
• To: 0x0000_0000.
Rewrote section 4.4.2.3.5, “Watchdog Timer/Debug Reset” and incorporated changes.
Rewrote section 4.4.2.3.5, “Watchdog Timer/Debug Reset to read:
The WDRS bit in the reset status register (SIU_RSR) is set when the watchdog timer or a debug request reset occurs.
A watchdog timer reset occurs and the WDRS bit is set when all the following conditions occur:
•
e200z6 core watchdog timer is enabled with the enable next watchdog timer (EWT)
•
Watchdog timer interrupt status (WIS) bits are set in the timer status register (TSR)
•
Watchdog reset control (WRC) field in the timer control register (TCR) is configured to reset
•
Time-out occurs
The debug tool can issue a debug reset command by writing 2’b10 to the RST bit {DBCR0[2:3]} register in the e200z6 core,
which sets the WDRS bit in the reset status register of the systems integration unit (SIU_RSR)
To determine if WDRS was set by a watchdog timer or debug reset, check the WRS field in the e200z6 core TSR.
The effect of a watchdog timer or debug reset request is the same on the reset controller.
The debug tool can also reset the device using one of the following methods:
•
Debug tool asserts the RESET signal on the RESET_b pin
•
Debug tool sets the software system reset (SSR) bit in the system reset control register (SIU_SRCR)
•
Debug tool writes a one to the software external reset (SER) bit in the system reset control register (SIU_SRCR) to
generate an external software reset
The device comes out of reset using the following sequence:
1.
Starting when the internal reset signal asserts, as indicated by RSTOUT asserting, the value on the WKPCFG pin
is applied. At the same time, the PLLCFG[0:1] values are applied only if RSTCFG is asserted.
2.
After the FMPLL is locked, the reset controller waits the predetermined number of clock cycles before negating
RSTOUT. When the clock count finishes, WKPCFG and BOOTCFG[0:1] are sampled. BOOTCFG[0:1] is only
sampled if RSTCFG asserts.
3.
The reset controller then waits 4 clock cycles before the negating RSTOUT, and the associated bits/fields are
updated in the SIU_RSR.
Refer to the e200z6 Core Guide for more information on the watchdog timer and debug operation.
Refer to Section 4.2.2, “Reset Output (RSTOUT).”
Summary of Contents for MPC5565
Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...
Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...
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Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...
