Freescale Semiconductor MPC5565, Reference Manual

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Reset
MPC5565 Microcontroller Reference Manual, Rev. 1.0
4-10 Freescale Semiconductor
The device comes out of reset using the following sequence:
1. Starting when the internal reset signal asserts, as indicated by RSTOUT asserting, the value on the
WKPCFG pin is applied. At the same time, the PLLCFG[0:1] values are applied only if RSTCFG
is asserted.
2. After the FMPLL is locked, the reset controller waits the predetermined number of clock cycles
before negating RSTOUT. When the clock count finishes, WKPCFG and BOOTCFG[0:1] are
sampled. BOOTCFG[0:1] is only sampled if RSTCFG asserts.
3. The reset controller then waits 4 clock cycles before the negating RSTOUT, and the associated
bits/fields are updated in the SIU_RSR.
Refer to the e200z6 Core Guide for more information on the watchdog timer and debug operation.
Refer to Section 4.2.2, “Reset Output (RSTOUT) .”
4.4.2.3.6 Checkstop Reset
When the e200z6 core enters a checkstop state, and the checkstop reset is enabled, the CRE bit in the
system reset control register (SIU_SRCR) is set and a checkstop reset occurs. Starting when the internal
reset signal asserts (RSTOUT), the value on the WKPCFG pin is applied; at the same time the
PLLCFG[0:1] values are applied if RSTCFG is asserted. After the FMPLL is locked, the reset controller
waits a predetermined number of clock cycles before negating RSTOUT.
Refer to Section 4.2.2, “Reset Output (RSTOUT) .”
When the clock count finishes, the WKPCFG and BOOTCFG[0:1] pins are sampled (the BOOTCFG[0:1]
pins are only sampled if RSTCFG is asserted). The reset controller then waits four clock cycles before the
negating RSTOUT, and updating the data in the SIU_RSR. In addition, the CRS bit is set, and all other
reset status bits in the SIU_RSR are cleared. Refer to e200z6 Core Guide for more information.
4.4.2.3.7 JTAG Reset
A system reset occurs when JTAG is enabled and either the EXTEST, CLAMP, or HIGHZ instructions are
executed by the JTAG controller. Starting at the assertion of the internal reset signal (as indicated by
assertion of RSTOUT), the value on the WKPCFG pin is applied; at the same time the PLLCFG[0:1]
values are applied if RSTCFG is asserted.
After the JTAG reset request has negated and the FMPLL is locked, the reset controller waits a
predetermined number of clock cycles before negating RSTOUT. When the clock count finishes the
WKPCFG and BOOTCFG[0:1] pins are sampled (note that the BOOTCFG[0:1] pins are sampled only if
RSTCFG is asserted), and the data is updated in the SIU_RSR. The reset source status bits in the SIU_RSR
are unaffected.
Refer to Section 4.2.2, “Reset Output (RSTOUT) .”
Refer to Chapter 23, “IEEE 1149.1 Test Access Port Controller (JTAGC) ,” for more information.