Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 18-75
18.4.3.6.2 Command Queue Completion Status
The end of queue flag, EQADC_FISRn[EOQF] (see Section 18.3.2.8, “eQADC FIFO and Interrupt Status
Registers 0–5 (EQADC_FISRn) ”) is asserted when the eQADC completes the transfer of a CFIFO entry
with an asserted EOQ bit. Software sets the EOQ bit in the last command message of a user-defined
command queue to indicate that this entry is the end of the queue. Refer to
Section 18.4.1.2, “Message
Format in eQADC ,” for information on command message formats. The transfer of entries bound for the
on-chip ADCs is considered completed when they are stored in the appropriate command buffer. The
transfer of entries bound for the external device is considered completed when the serial transmission of
the entry is completed.
The command with a EOQ bit asserted is valid and is transferred. When EQADC_CFCRn[EOQIE] (refer
to
Section 18.3.2.6, “eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn) ”) and
EQADC_FISRn[EOQF] are asserted, the eQADC generates an end of queue interrupt request.
7 TRIGGERED
(11)
IDLE
(0b00)
• CFIFO in single-scan mode, eQADC detects the EOQ bit
asserted at end of command transfer, and CFIFO mode is
not modified to disabled, OR
• CFIFO, in single-scan level trigger mode, and the gate
closes while no commands are being transferred from the
CFIFO, and CFIFO mode is not modified to disabled, OR
• CFIFO, in single-scan level trigger mode, and eQADC
detects a closed gated at end of command transfer, and
CFIFO mode is not modified to disabled, OR
• CFIFO mode is modified to disabled mode and CFIFO was
not transferring commands.
• CFIFO mode is modified to disabled mode while CFIFO was
transferring commands, and CFIFO completes or aborts the
transfer.
8 WAITING FOR
TRIGGER
(0b10)
• CFIFO in single or continuous-scan edge trigger mode,
eQADC detects the pause bit asserted at the end of
command transfer, the EOQ bit in the same command is
negated, and CFIFO mode is not modified to disabled, OR
• CFIFO in continuous-scan edge trigger mode, eQADC
detects the EOQ bit asserted at the end of command
transfer, and CFIFO mode is not modified to disabled, OR
• CFIFO, in continuous-scan level trigger mode, and the gate
closes while no commands are being transferred from the
CFIFO, and CFIFO mode is not modified to disabled, OR
• CFIFO, in continuous-scan level trigger mode, and eQADC
detects a closed gated at end of command transfer, and
CFIFO mode is not modified to disabled.
9 TRIGGERED
(0b11)
• No event to switch to IDLE or WAITING FOR TRIGGER
status has happened.
Table 18-45. Command FIFO Status Switching Condition (continued)
No.
From Current
CFIFO Status
(CFS)
To New CFIFO
Status (CFS)
Status Switching Condition