Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
17-32 Freescale Semiconductor
17.4.5.2 eTPU Channel Data Transfer Request Status Register (ETPU_CDTRSR)
Data transfer request status from all channels are grouped in ETPU_CDTRSR. The bits are mirrored by
the channels’ status/control registers. For more information on data transfers and channel control registers,
refer to the
eTPU Reference Manual .
In the MPC5566, eTPU A channels [0:2,12:15,28:29] are connected to the
DMA; in the MPC5565, eTPU channels [0:2, 14:15] are DMA connected.
The data transfer request lines that are not connected to the DMA controller
are left disconnected and do not generate transfer requests, even if their
request status bits are asserted in registers ETPU_CDTRSR and
ETPU_C
n SCR. Channels that are not connected can still have their status
bits (DTRS n ) cleared by writing a 1 to the appropriate field.
Address: Base + 0x0000_0200 (eTPU A) Access: R/W1c
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R CIS31 CIS30 CIS29 CIS28 CIS27 CIS26 CIS25 CIS24 CIS23 CIS22 CIS21 CIS20 CIS19 CIS18 CIS17 CIS16
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CIS15 CIS14 CIS13 CIS12 CIS11 CIS10 CIS9 CIS8 CIS7 CIS6 CIS5 CIS4 CIS3 CIS2 CIS1 CIS0
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-14. eTPU Channel Interrupt Status Register (ETPU_CISR)
Table 17-15. ETPU_CISR Field Descriptions
Field Description
0–31
CIS
n
Channel n interrupt status.
0 indicates that channel n has no pending interrupt to the host core.
1 indicates that channel n has a pending interrupt to the host core.
To clear a status bit, the host must write 1 to it.
For details about interrupts refer to the
eTPU Reference Manual .