Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
16-10 Freescale Semiconductor
16.3.1.3 eMIOS Output Update Disable Register (EMIOS_OUDR)
The EMIOS_OUDR serves to disable transfers from the A2 to the A1 channel registers and from the B2
to the B1 channel registers when values are written to these registers, and the channel is running in
modulus counter (MC) mode or an output mode.
The following table describes the fields in the eMIOS output update disable register:
Address: Base + 0x0004 Access: R/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 F23 F22 F21 F20 F19 F18 F17 F16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 16-3. eMIOS Global Flag Register (EMIOS_GFR)
Address: Base + 0x0008 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0
OU23 OU22 OU21 OU20 OU19 OU18 OU17 OU16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
OU15 OU14 OU13 OU12 OU11 OU10 OU9 OU8 OU7 OU6 OU5 OU4 OU3 OU2 OU1 OU0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 16-4. eMIOS Output Update Disable Register (EMIOS_OUDR)
Table 16-7. EMIOS_OUDR Field Descriptions
Field Description
0–7 Reserved.
8–31
OU n
Channel n output update disable. When running in MC mode or an output mode, values are written to registers A2
and B2. OU n bits are used to disable transfers from registers A2 to A1 and B2 to B1. Each bit controls one channel.
0 Transfer enabled. Depending on the operating mode, transfer occurs immediately or in the next period. Unless
stated otherwise, transfer occurs immediately.
1 Transfers disabled