Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-27
19.3.2.9 DSPI Receive FIFO Registers 0–3 (DSPI x _RXFR n )
The DSPI x _RXFR n registers provide visibility into the RX FIFO for debugging purposes. Each register is
an entry in the RX FIFO. The DSPI x _RXFR registers are read-only. Reading the DSPI x _RXFR n registers
does not alter the state of the RX FIFO. The device uses four registers to implement the RX FIFO, that is
DSPI
x _RXFR0–DSPI x _RXFR3 are used.
The following table describes the field in the DSPI receive FIFO register:
Address:
Base + 0x007C (DSPI
x _RXFR0)
Base + 0x0080 (DSPI x _RXFR1)
Base + 0x0084 (DSPI x _RXFR2)
Base + 0x0088 (DSPI x _RXFR3)
Access: R/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 19-11. DSPI Receive FIFO Registers 0–3 (DSPI x _RXFR n )
Table 19-11. DSPI x _RXFR n Field Description
Field Description
0–15 Reserved, must be cleared.
16–31
RXDATA
[15:0]
Receive data. Contains the received SPI data.