Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-51
Figure 19-28 shows the CSI serialization logic.
Figure 19-28. CSI Serialization Diagram
The parallel inputs signal states are latched into the DSPI x _SDR on the rising edge of every system clock
and serialized based on the transfer initiation control settings in the DSPI x _DSICR. For more information
on the DSPI x _SDR. SPI frames written to the TX FIFO have priority over DSI data from the DSPI x _SDR
and are transferred at the next frame boundary. A copy of the most recently transferred DSI frame is stored
in the DSPI
x _COMPR. The transfer priority logic selects the source of the serialized data and asserts the
chip select signal.
Refer to Section 19.3.2.11, “DSPI DSI Serialization Data Register (DSPIx_SDR) .”
19.4.5.2 CSI Deserialization
The deserialized frames in CSI configuration go into the DSPI x _SDR or the RX FIFO based on the transfer
priority logic. When DSI frames are transferred the returned frames are deserialized and latched into the
DSPI
x _DDR. When SPI frames are transferred the returned frames are deserialized and written to the RX
FIFO.
SOUTx
Parallel
DSI control
register
DSI transmit
comparison register
Clock
logic
0 1 • • • • • 15
Shift register DSI serialization
data register
Control
logic
SCKx
inputs
PCSx (SPI)
PCSy (DSI)
16
16
16
16
Transfer
Slave bus interface
16
TX FIFO
(P_IN)
priority logic