System Integration Unit (SIU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor
6-115
6.4.1.2
Pad Configuration
The pad configuration registers (SIU_PCR) in the SIU allow software control over the following electrical
characteristics of the external pads:
•
Weak pullup/down enable/disable
•
Weak pullup/down selection
•
Slew-rate selection for outputs
•
Drive strength selection for outputs
•
Input buffer enable (when direction is configured for output)
•
Input hysteresis enable/disable
•
Open drain/push-pull output selection
•
Multiplexed function selection
•
Data direction selection
The pad configuration registers are provided to allow centralized control over external pins that are shared
by more than one module. Each pad configuration register controls a single pin.
6.4.2
Reset Control
The reset controller logic is located in the SIU. Refer to
Section 6.2.1.1, “Reset Input (RESET)
Section 6.2.1.2, “Reset Output (RSTOUT)
for details on the reset operations.
6.4.2.1
RESET Pin Glitch Detect
The reset controller provides a glitch detect feature on the RESET pin. If the reset controller detects that
the RESET pin is asserted for more than two clock cycles, the event is latched. After the latch is set, if the
RESET pin is negated before 10 clock cycles is reached, the reset controller sets the RGF bit without
affecting any of the other bits in the reset status register (SIU_RSR). The latch is cleared when the RGF
bit is set or a valid reset is recognized. The RGF bit remains set until cleared by a software or the RESET
signal asserts for 10 clock cycles. The reset controller does not respond to assertions of the RESET pin if
a reset cycle is already being processed.
6.4.3
External Interrupt
There are sixteen external interrupt inputs IRQ[0]–IRQ[15] to the SIU. The IRQ inputs can be configured
for rising-edge events, falling-edge events, or both. Each IRQ input has a flag bit in the external interrupt
status register (SIU_EISR). The flag bits for the IRQ[4:15] inputs are OR’ed together to form one interrupt
request to the interrupt controller (OR function performed in the integration glue logic). The flag bits for
the IRQ[0:3] inputs can generate either an interrupt request to the interrupt controller or a DMA transfer
request to the DMA controller.
shows the DMA and interrupt request connections to the interrupt and DMA controllers.
Summary of Contents for MPC5565
Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...
Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...
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Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...
