Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Serial Communication Interface (eSCI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 20-29
In Figure 20-18 the verification samples RT3 and RT5 determine that the first low detected was noise and
not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag
is not set because the noise occurred before the start bit was found.
Figure 20-18. Start Bit Search Example
20.4.5.4 Framing Errors
If the data recovery logic sets the framing error flag, ESCI x _SR[FE], it does not detect a logic 1 where the
stop bit should be in an incoming frame. A break character also sets the FE flag because a break character
has no stop bit. The FE flag is set at the same time that the RDRF flag is set.
20.4.5.5 Baud Rate Tolerance
When a transmitting device operates at a baud rate below or above the receiver baud rate, accumulated
bit-time misalignment can cause one of the three stop bit data samples (RT8, RT9, and RT10) to fall outside
the stop bit. A noise error occurs if the RT8, RT9, and RT10 samples are not all the same logical values. A
framing error occurs if the receiver clock is misaligned such that the majority of the RT8, RT9, and RT10
stop bit samples are a logic zero.
The receiver samples an incoming frame and re-synchronizes the RT clock on any valid falling edge within
the frame. Re-synchronization within frames corrects a misalignment between transmitter bit times and
receiver bit times.
RT clock
1 1 1 0 1 1 1 0 0 0
RT1
RT1
RT1 RT2
RT1
RT4
RT3 RT5
RT1 RT2 RT4 RT6 RT8 RT10 RT12 RT14 RT16 RT2
RT1 RT3 RT5 RT7 RT9 RT11 RT13 RT15 RT1 RT3
Reset
RT clock
RT clock
count
RXD input
signal
samples
Start bit LSB
0 0 0 0