Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 17-11
17.2.3 Debug Mode
The core debugs eTPU code, accessing special trace/debug features via Nexus interface:
— Hardware breakpoint/watchpoint setting
— Access to internal registers
— Single-step execution
— Forced instruction execution
— Software breakpoint insertion and removal
17.2.4 Module Disable Mode
eTPU engine clocks are stopped through a register write to ETPU_ECR bit MDIS, saving power. Input
sampling stops. eTPU engines can be in stop mode independently. Module disable mode stops only the
engine clock, so that the shared BIU and global channel registers can be accessed, and interrupts and DMA
requests can be cleared and enabled/disabled. An engine only enters module disable mode when any
currently running thread is finished.
These modes are loosely selected: there is no unique register field or signals to choose between them.
Some features of one mode can be used with features of other modes.
17.2.5 eTPU Mode Selection
User and user configuration are the production operating modes, and differ from each other only in access
to SCM.
Module disable mode is entered by setting ETPU_ECR[MDIS]. eTPU engines can be individually stopped
(there is one ETPU_ECR for each engine).
17.3 External Signal Description
17.3.1 Overview
There are 65 external signals in each eTPU engine:
• 32 channel input signals,
• 32 channel output signals,
• TCRCLK clock input,
There are a total of 65 external signals in a single-engine system, or 130 external signals in a dual-engine
system. There are four internal output disable signals for each eTPU engine that implement the output
disable feature needed for motor control.
Refer to 16.2.1.1, “Output Disable Input—eMIOS Output Disable Input Signals ,” for more information.
17.3.2 Output and Input Channel Signals
Each eTPU channel has an input and output associated with it, and these can be connected to external pins
or wired internally to other peripheral devices. As shown in
Chapter 19, “Deserial Serial Peripheral