Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-39
that is returned when DSPI x _POPR is read. The POPNXTPTR field is incremented every time the
DSPI x _POPR is read. POPNXTPTR rolls over every four frames on the MCU.
19.4.3.5.1 Filling the RX FIFO
The RX FIFO is filled with the received SPI data from the shift register. While the RX FIFO is not full,
SPI frames from the shift register are transferred to the RX FIFO. Every time an SPI frame is transferred
to the RX FIFO the RX FIFO counter is incremented by one.
If the RX FIFO and shift register are full and a transfer is initiated, the RFOF bit in the DSPI x _SR is set
indicating an overflow condition. Depending on the state of the ROOE bit in the DSPI x _MCR, the data
from the transfer that generated the overflow is ignored or put in the shift register. If the ROOE bit is set,
the incoming data is put in the shift register. If the ROOE bit is cleared, the incoming data is ignored.
19.4.3.5.2 Draining the RX FIFO
Host software or the eDMA can remove (pop) entries from the RX FIFO by reading the DSPI x _POPR. A
read of the DSPI x _POPR decrements the RX FIFO counter by one. Attempts to pop data from an empty
RX FIFO are ignored, the RX FIFO counter remains unchanged. The data returned from reading an empty
RX FIFO is undetermined.
Refer to Section 19.3.2.7, “DSPI POP RX FIFO Register (DSPIx_POPR) ” for more information on
DSPI x _POPR.
When the RX FIFO is not empty, the RX FIFO drain flag (RFDF) in the DSPI x _SR is set. The RFDF bit
is cleared when the RX_FIFO is empty and the eDMA controller indicates that a read from DSPI x _POPR
is complete; alternatively the RFDF bit can be cleared by the host writing a 1 to it.
19.4.4 Deserial Serial Interface (DSI) Configuration
The DSI configuration supports pin count reduction by serializing parallel input signals or register bits and
shifting them out in an SPI-like protocol. The received serial frames are converted to a parallel form
(deserialized) and placed on the parallel output signals or in a register. The various features of the DSI
configuration are set in the DSPI
x _DSICR. For more information on the DSPI x _DSICR. The DSPI is in
DSI configuration when the DCONF field in the DSPI x _MCR is 0b01.
Refer to Section 19.4.7, “Transfer Formats ” for a description of the timing and transfer protocol.
Refer to Section 19.3.2.10, “DSPI DSI Configuration Register (DSPIx_DSICR) .”
The DSI frames can be from 4 to 16 bits long. With multiple transfer operation (MTO), the DSPI supports
serial chaining of DSPI modules within the MCU to create DSI frames consisting of concatenated bits
from multiple DSPIs. The DSPI also supports parallel chaining allowing several DSPIs and off-chip SPI
devices to share the same serial communications clock (SCK) and peripheral chip select (PCS) signals.
Refer to Section 19.4.4.7, “Multiple Transfer Operation (MTO) ,” for details on the serial and parallel
chaining support.