Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
19-46
Freescale Semiconductor
19.4.4.7
Multiple Transfer Operation (MTO)
In DSI configuration the MTO feature allows for multiple DSPIs within the MCU to be chained together
in a parallel or serial configuration. The parallel chaining allows multiple DSPIs internal to the MCU and
multiple SPI devices external to the MCU to share SCK and PCS signals thereby saving pins. The serial
chaining allows bits from multiple DSPIs to be concatenated into a single DSI frame. MTO is enabled by
setting the MTOE bit in the DSPI
x
_DSICR.
In parallel and serial chaining there is one bus master and multiple bus slaves. The bus master initiates and
controls the transfers, but the DSPI slaves generate trigger signals for the bus DSPI master when an
internal condition in the slave warrants a transfer. The DSPI slaves also propagate triggers from other
slaves to the master. When a DSPI slave detects a trigger signal on its
ht
input, the slave generates a trigger
signal on the MTRIG output.
The SIU_DISR must be configured to use serial or parallel chaining.
19.4.4.7.1
Internal Muxing/SIU Support for Serial and Parallel Chaining
To support MTO, each DSPI in the device has multiplexers on the SIN
x
, SS
x
, SCK
x
, and
ht
inputs. The
internal multiplexers are controlled by registers in the SIU block.
Refer to
Section 6.4.5.3, “Multiplexed Inputs for DSPI Multiple Transfer Operation
.”
shows DSPI B and the multiplexers in the IMUX subblock of the SIU. The SOUT
x
, MTRIG,
SCK
x
and PCS
x
0 outputs from the other two DSPIs connect to the multiplexers on the DSPI B inputs.
DSPI B, DSPI C and DSPI D have similar multiplexers on their inputs.
eTPUA output channel 29
10
10
Input 3 on IMUX for external IRQ[8]
eTPUA output channel 28
11
11
Input 3 on IMUX for external IRQ[9]
eTPUA output channel 27
12
12
Input 3 on IMUX for external IRQ[10]
eTPUA output channel 26
13
13
Input 3 on IMUX for external IRQ[11]
eTPUA output channel 25
14
14
eMIOS input channel 15,
Input 3 on IMUX for external IRQ[12]
eTPUA output channel 24
15
15
eMIOS input channel 14,
Input 3 on IMUX for external IRQ[13]
Table 19-21. DSPI D Connectivity Table (continued)
Connected to:
DSPI D
IN[
n
]
DSPI D
OUT[
n
]
Connected to:
Summary of Contents for MPC5565
Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...
Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...
Page 35: ...MPC5565 Reference Manual Rev 1 0 16 Freescale Semiconductor...
Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...
