Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-65
19.4.9.4 Transmit FIFO Underflow Interrupt Request (TFUF)
The transmit FIFO underflow request indicates that an underflow condition in the TX FIFO has occurred.
The transmit underflow condition is detected only for DSPI modules operating in slave mode and SPI
configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in slave mode and SPI
configuration is empty, and a transfer is initiated from an external SPI master. If the TFUF bit is set while
the TFUF_RE bit in the DSPI
x _RSER is set, an interrupt request is generated.
19.4.9.5 Receive FIFO Drain Interrupt or DMA Request (RFDF)
The receive FIFO drain request indicates that the RX FIFO is not empty. The receive FIFO drain request
is generated when the number of entries in the RX FIFO is not zero, and the RFDF_RE bit in the
DSPI
x _RSER is set. The RFDF_DIRS bit in the DSPI x _RSER selects whether a DMA request or an
interrupt request is generated.
19.4.9.6 Receive FIFO Overflow Interrupt Request (RFOF)
The receive FIFO overflow request indicates that an overflow condition in the RX FIFO has occurred. A
receive FIFO overflow request is generated when RX FIFO and shift register are full and a transfer is
initiated. The RFOF_RE bit in the DSPI
x _RSER must be set for the interrupt request to be generated.
Depending on the state of the ROOE bit in the DSPI x _MCR, the data from the transfer that generated the
overflow is either ignored or shifted in to the shift register. If the ROOE bit is set, the incoming data is
shifted in to the shift register. If the ROOE bit is negated, the incoming data is ignored.
19.4.9.7 FIFO Overrun Request (TFUF) or (RFOF)
The FIFO overrun request indicates that at least one of the FIFOs in the DSPI has exceeded its capacity.
The FIFO overrun request is generated by logically OR’ing together the RX FIFO overflow and TX FIFO
underflow signals.
19.4.10 Power Saving Features
The DSPI supports two power-saving strategies:
• Module disable mode—clock gating of non-memory mapped logic
• Clock gating of slave interface signals and clock to memory-mapped logic
19.4.10.1 Module Disable Mode
Module disable mode is a module-specific mode that the DSPI can enter to save power. Host software can
initiate the module disable mode by writing a 1 to the MDIS bit in the DSPI
x _MCR. In module disable
mode, the DSPI is in a dormant state, but the memory mapped registers are still accessible. Certain read
or write operations have a different affect when the DSPI is in the module disable mode. Reading the RX
FIFO pop register does not change the state of the RX FIFO. Likewise, writing to the TX FIFO push
register does not change the state of the TX FIFO. Clearing either of the FIFOs does not have any effect
in the module disable mode. Changes to the DIS_TXF and DIS_RXF fields of the DSPI
x _MCR does not
have any affect in the module disable mode. In the module disable mode, all status bits and register flags