Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 16-37
Figure 16-24. Double-action Output Compare with FLAG Set on Both Matches
16.4.4.4.7 Pulse/Edge Accumulation Mode (PEA)
The following table lists the pulse/edge accumulation mode settings:
The PEA mode returns the time taken to detect a desired number of input events. MODE[6] bit selects
between continuous or single shot operation.
After writing to register A1, the internal counter is cleared on the first input event, ready to start counting
input events and the selected timebase is latched into register B2. On the match between the internal
counter and register A1, a counter bus capture is triggered to register A2 and B2. The data previously held
in register B2 is transferred to register B1 and the FLAG bit is set to indicate that an event has occurred.
The desired time interval can be determined by subtracting register B1 from A2. Registers
EMIOS_CADR
n and EMIOS_CBDR n return the values in register A2 and B1, respectively.
To guarantee coherent access, reading EMIOS_CADR n disables transfers between B2 and B1. These
transfers are disabled until the next read of the EMIOS_CBDR n register. Reading the EMIOS_CBDR n
register re-enables transfers from B2 to B1, to take effect at the next transfer event, as described above.
1
Triggering of the counter clock (an input event) is done by a rising or falling edge or both edges on the
input pin. The polarity of the triggering edge is selected by the EDSEL and EDPOL bits in EMIOS_CCR
n .
Table 16-20. PEA Operating Mode
MODE[0:6] Unified Channel PEA Operating Mode
0b0001000 Pulse/edge accumulation (continuous)
0b0001001 Pulse/edge accumulation (single shot)
1. If B1 was not updated due to B2 to B1 transfer being disabled after reading register EMIOS_CADR n , further
EMIOS_CADR n and EMIOS_CBDR n reads do not return coherent data until a new bus capture is triggered to registers
A2 and B2. The capture event is indicated when the channel FLAG asserts. If enabled, the FLAG also generates an inter-
rupt.
Selected
counter bus
FLAG
set event
A1 match
0xxxxxxx 0x001000 0x001000 0x001000
Notes:
1
Writing EMIOS_CADR n writes to A1.
2
Writing EMIOS_CBDR n writes to B1.
MODE[6] = 1 B1 match B1 match
0xxxxxxx 0x001100 0x001100 0x001100
A1 match
Update to
A1 and B1
Output
flip-flop
A1 value
1
B1 value
2
A2 value transferred to A1 according to OU n bit.
B2 value transferred to B1 according to OU n bit.
0x000500 0x001000 0x001100 0x001000 0x001100