Freescale Semiconductor MPC5565, Reference Manual

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External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 12-51
Figure 12-32 shows an example of the termination signals protocol for back-to-back reads to two different
slave devices who properly take turns driving the termination signals. This assumes a system using slave
devices that drive termination signals.
Figure 12-32. Termination Signals Protocol Timing Diagram
T he EBI drives address and control signals an extra cycle because it uses a latched version of TA
*
Th is is the earliest that the EBI can start another transfer, in the case of continuing a set of small accesses.
For all other cases, an extra cycle is needed before the EBI can start another TS.
**
CLKOUT
BB
TS
DATA[0:31]
TA, TEA
ADDR[8:31]
RD_WR
Slave 1 Slave 2
* *
**
(1 cycle delayed) to terminate the cycle. An external master is not required to do this.
Slave 1
negates
acknowledge
signals and
‘turns off’
Slave 2
negates
acknowledge
signals and
‘turns off’
Slave 2
allowed to
drive
acknowledge
signals
Slave 1
allowed to
drive
acknowledge
signals