Freescale Semiconductor MPC5565, Reference Manual

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MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor 10
When the device is in the checkstop state, processing is suspended and cannot resume without
a reset. When a debug request is presented to the core while it is in the checkstop state, the core
temporarily exits the checkstop state and enters debug mode. When debug mode exits, the core
re-enters the checkstop state.
If the external interrupt bit in the MSR is enabled, data or instruction stage interrupts are reported
when the ECC errors are a result of CPU accesses, regardless of whether non-correctable
reporting is enabled.
ECC errors generated by other masters (eDMA, etc.) do not generate data or instruction storage
exceptions, and the ECSM is used to report these errors. You must initialize the ECSM to enable
non-correctable reporting with interrupt generation to detect and report ECC interrupts from the
ECSM.
Error reporting details can be independently enabled for flash memory and SRAM. To enable
non-correctable error reporting and save the error details for:
• SRAM—set the ERNCR bit in the ECSM Error Configuration Register (ECSM_ECR).
• Flash—set the EFNCR bit in ECSM_ECR.
When these bits are set and a non-correctable ECC error occurs, error information is recorded
in other ECSM registers and an interrupt request is generated on vector 9 of the interrupt
controller (INTC).
• CPU data access error—Generates data storage exception (IVOR2).
• CPU instruction access error—Generates instruction storage exception (IVOR3).
• Vector 9 of INTC enabled—Generates an external exception (IVOR4)
Section 11.4.3.3, "FM
Calibration Routine"/ Page
11-29
Correct the equation at the end of the third paragraph: change value of M from 640 to 480.
Table 6-135, “SIU_DISR
Field Descriptions”/ Page
6-108
• Bit 14-15–TRIGSELB: Correct the input select description as follows:
00: Replace the term “Invalid value” with “No Trigger”
01: Replace the term “Invalid value” with “No Trigger”
• Bit 22-23–TRIGSELC: Correct the input select description as follows
00: Replace the term “Invalid value” with “No Trigger”
01: Replace the term “Invalid value” with “No Trigger”
• Bit 30-31–TRIGSELD: Correct the input select description as follows
00: Replace the term “Invalid value” with “No Trigger”
01: Replace the term “Invalid value” with “No Trigger”
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description