Freescale Semiconductor MPC5565, Reference Manual

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Preface
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 21-21
21.3.3.8 Interrupt Masks High Register (ICAN x _IMRH)
CAN x _IMRH allows any number of a range of 32 message buffer interrupts to be enabled or disabled. It
contains one interrupt mask bit per buffer, enabling the CPU to determine which buffer generates an
interrupt after a successful transmission or reception (that is, when the corresponding IFRH bit is set).
24
IDLE
CAN bus IDLE state. This status bit indicates when CAN bus is in IDLE state.
0 No such occurrence
1 CAN bus is now IDLE
25
TXRX
Current FlexCAN2 status (transmitting/receiving). This status bit indicates if FlexCAN2 is transmitting or
receiving a message when the CAN bus is not in IDLE state. This bit has no meaning when IDLE is
asserted.
0 FlexCAN2 is receiving a message (IDLE = 0)
1 FlexCAN2 is transmitting a message (IDLE = 0)
26–27
FLTCONF[0:1]
Fault confinement state. This status bit indicates the confinement state of the FlexCAN2 module. If the
LOM bit in the CAN
x _CR is asserted, the FLTCONF field will indicate “Error Passive”. Since the CAN x _CR
is not affected by soft reset, the FLTCONF field will not be affected by soft reset if the LOM bit is asserted.
00 Error active
01 Error passive
1X Bus off
28 Reserved.
29
BOFFINT
Bus off interrupt. This status bit is set when FlexCAN2 is in the bus off state. If CAN x _CR[BOFFMSK] is
set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
0 No such occurrence
1 FlexCAN2 module is in ‘Bus Off’ state
30
ERRINT
Error interrupt. This status bit indicates that at least one of the error bits (bits 16-21) is set. If
CAN
x _CR[ERRMSK] is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1.
Writing 0 has no effect.
0 No such occurrence
1 Indicates setting of any error bit in the CAN
x _ESR
31 Reserved.
Address: Base + 0x0024 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R BUF
63M
BUF
62M BUF
61M BUF
60M BUF
59M BUF
58M BUF
57M BUF
56M BUF
55M BUF
54M BUF
53M BUF
52M BUF
51M BUF
50M BUF
49M BUF
48M
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R BUF
47M
BUF
46M BUF
45M BUF
44M BUF
43M BUF
42M BUF
41M BUF
40M BUF
39M BUF
38M BUF
37M BUF
36M BUF
35M BUF
34M BUF
33M BUF
32M
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 21-10. Interrupt Masks High Register (CAN x _IMRH)
Table 21-12. CAN x _ESR Field Descriptions (continued)
Field Description