Freescale Semiconductor MPC5565, Reference Manual

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Reset
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 4-7
4.4.2 Reset Sources
4.4.2.1 FMPLL Lock
A loss of lock of the FMPLL can cause a reset (provided the SIU is enabled by the
FMPLL_SYNCR[LOLRE] bit). Furthermore, reset remains asserted, regardless of the reset source, until
after the FMPLL locks.
4.4.2.2 Flash High Voltage
There is no flash access gating signal implemented in this device. However, the device is held in reset for
a long enough period of time to guarantee that high voltage circuits are reset and stabilized and that flash
memory is accessible.
4.4.2.3 Reset Source Descriptions
For the following reset source descriptions refer to the reset flow diagrams in Figure 4-5 and Figure 4-6 .
Figure 4-5 shows the reset flow when RESET asserts. Figure 4-6 shows the internal reset processing for
all reset sources.
4.4.2.3.1 Power-on Reset
The power-on reset (POR) circuit is designed to detect a POR event and ensure that the RESET signal is
correctly sensed. The POR is not designed to detect falling power supply voltages. Provide monitoring for
external supply. The output signals from the power-on reset circuits are active low signals. All power-on
reset output signals are combined into one POR signal at the V
DD
level and input to the reset controller.
Although assertion of the power-on reset signal causes reset, the RESET pin must be asserted during a
power-on reset to guarantee proper operation of the MCU.
The PLLCFG[0:1] and RSTCFG pins determine the configuration of the FMPLL. If the RSTCFG pin is
asserted at the negation of RSTOUT, the PLLCFG[0:1] pins set the operating mode of the FMPLL. If
RSTCFG is asserted anytime during the assertion of RSTOUT, the FMPLL switches to the mode specified
by the PLLCFG[0:1] pins. The values on the RSTCFG and the PLLCFG[0:1] pins must be kept constant
after RSTCFG is asserted to avoid transient mode changes in the FMPLL. If RSTCFG is in the negated
state at the negation of RSTOUT, the FMPLL defaults to enabled with a crystal reference.
Refer to Chapter 11, “Frequency Modulated Phase Locked Loop and System Clocks (FMPLL) ,” for more
details on the operation of the FMPLL and the PLLCFG[0:1] pins.
The signal on the WKPCFG pin determines whether weak pullup or pulldown devices are enabled after
reset on the eTPU and eMIOS pins. The WKPCFG pin is applied starting at the assertion of the internal
reset signal, as indicated by the assertion of RSTOUT.
Refer to Figure 4-4 and see Chapter 2, “Signal Description ,” for information on WKPCFG and RSTOUT.
After the RESET input pin is negated, the reset controller checks if the FMPLL is locked. The internal
reset signal and RSTOUT are kept asserted until the FMPLL is locked. After the FMPLL is locked, the
reset controller waits an additional predetermined number of clock cycles before negating the RSTOUT
pin. The WKPCFG and BOOTCFG[0:1] pins are sampled 4 clock cycles before the negation of RSTOUT,