Freescale Semiconductor MPC5565, Reference Manual

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Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
11-28 Freescale Semiconductor
— Write the RFD control field to 1 + the desired final RFD value (RFD must be greater than one
to protect from overshoot).
2. Wait for the FMPLL to lock by monitoring the FMPLL_SYNSR[LOCK] bit. Refer to
Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR) ,” for memory synchronization
between changing FMPLL_SYNCR[MFD] and monitoring the lock status.
3. If using the frequency modulation feature, then:
a) Enable FM by setting FMPLL_SYNCR[DEPTH] = 1 or 2.
b) Also set FMPLL_SYNCR[RATE] if not done previously in step 2.
4. Calibration starts. After calibration is done, then the FMPLL re-locks. Wait for the FMPLL to
re-lock by monitoring the FMPLL_SYNSR[LOCK] bit.
5. Verify FM calibration completed and was successful by testing the FMPLL_SYNSR[CALDONE]
and FMPLL_SYNSR[CALPASS] bitfields.
6. If FM calibration did not complete or was not successful, attempt again by going back to step 1.
7. Initialize the FMPLL to the desired final system frequency by changing FMPLL_SYNCR[RFD].
Note that the FMPLL does not need to re-lock when only changing the RFD.
8. Re-enable LOLIRQ.
NOTE
This first register write causes the FMPLL to switch to an initial frequency
which is less than the final one. Keeping the change of frequency to a lower
initial value helps minimize the current surge to the external power supply
caused by change of frequency. The last step changes the RFD to get the
final frequency.
NOTE
Changing the MFD or PREDIV values causes the FMPLL to perform a
search for the lock frequency that results in the system clock frequency
changing rapidly across the complete frequency range. All MCU
peripherals, including the external bus, are subjected to this frequency
sweep. Operation of timers and serial communications during this search
sequence produces unpredictable results.
Note that the frequency modulation system is dependent upon several factors: the accuracies of the
V
DDSYN
/V
SSSYN
voltage, of the crystal oscillator frequency, and of the manufacturing variation.
For example, if a 5% accurate supply voltage is used, then a 5% modulation depth error results. If the
crystal oscillator frequency is skewed from 8 MHz, the resulting modulation frequency is proportionally
skewed. Finally, the error due to the manufacturing and environment variation alone can cause the
frequency modulation depth error to be greater than 20%.