Freescale Semiconductor MPC5565, Reference Manual

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Error Correction Status Module (ECSM)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
8-6 Freescale Semiconductor
NOTE
The only allowable values for the 2 control bit enables {FRCNCI, FR1NCI}
are {0,0}, {1,0} and {0,1}. The value {1,1} results in undefined behavior.
Base + 0x004A Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0
FRC
NCI
FR1
NCI
0
ERRBIT[0:6]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 8-3. ECC Error Generation (ECSM_EEGR) Register
Table 8-5. ECSM_EEGR Field Definitions
Field Description
0–5 Reserved
6
FRCNCI
Force internal SRAM continuous noncorrectable data errors.
0 No internal SRAM continuous 2-bit data errors are generated.
1 2-bit data errors in the internal SRAM are continuously generated.
The assertion of this bit forces the internal SRAM controller to create 2-bit data errors, as defined by the bit position
specified in ERRBIT[0:6] and the overall odd parity bit, continuously on every write operation.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by
ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
7
FR1NCI
Force internal SRAM one noncorrectable data errors.
0 No internal SRAM single 2-bit data errors are generated.
1 One 2-bit data error in the internal SRAM is generated.
The assertion of this bit forces the internal SRAM controller to create one 2-bit data error, as defined by the bit
position specified in ERRBIT[0:6] and the overall odd parity bit, on the first write operation after this bit is set.
The normal ECC generation takes place in the internal SRAM controller, but then the polarity of the bit position
defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly
re-enable the error generation logic.
8 Reserved
9–15
ERRBIT
Error bit position. Defines the bit position which is complemented to create the data error on the write operation. The
bit specified by this field plus the odd parity bit of the ECC code are inverted.
The internal SRAM controller follows a vector bit ordering scheme where LSB=0. Errors in the ECC syndrome bits
can be generated by setting this field to a value greater than the internal SRAM width. The following association
between the ERRBIT field and the corrupted memory bit is defined:
if ERRBIT = 0, then RAM[0] is inverted
if ERRBIT = 1, then RAM[1] is inverted
...
if ERRBIT = 63, then RAM[63] is inverted
if ERRBIT = 64, then ECC Parity[0] is inverted
if ERRBIT = 65, then ECC Parity[1] is inverted
...
if ERRBIT = 71, then ECC Parity[7] is inverted
For ERRBIT values greater than 71, no bit position is inverted.