Freescale Semiconductor MPC5565, Reference Manual

Page: 339 / 1153

Enhanced Direct Memory Access (eDMA)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
9-14 Freescale Semiconductor
9.2.2.8 eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
The EDMA_CEEIR provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_EEIRL to disable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EDMA_EEIRL to be cleared. Setting bit 1 (CEEI
n ) provides a global clear
function, forcing the entire contents of the EDMA_EEIRL to be zeroed, disabling error interrupts for all
channels. Reads of this register return all zeroes.
Address: Base + 0x001A Access: User W/O
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W SEEI[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 9-8. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
Table 9-8. EDMA_SEEIR Field Descriptions
Field Description
0 Reserved.
1–7
SEEI[0:6]
Set enable error interrupt.
0–31 Set corresponding bit in EDMA_EIRRL
32–63 Reserved
64–127 Set all bits in EDMA_EEIRH or EDMA_EEIRL
Note: Bit 2 (SEEI1) is not used.
Address: Base + 0x001B Access: User W/O
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W CEEI[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 9-9. eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
Table 9-9. EDMA_CEEIR Field Descriptions
Field Description
0 Reserved.
1–7
CEEI[0:6]
Clear enable error interrupt.
0–31 Clear corresponding bit in EDMA_EEIRL
32–63 Reserved
64–127 Clear all bits in EDMA_EEIRH or EDMA_EEIRL
Note: Bit 2 (CEEI1) is not used.