Freescale Semiconductor MPC5565, Reference Manual

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e200z6 Core Complex
MPC5565 Microcontroller Reference Manual, Rev. 1.0
3-30 Freescale Semiconductor
Machine check IVOR 1 ME CSSR[0:1] • Machine check exception and MSR[ME] =1
• ISI, ITLB error on first instruction fetch for an exception
handler
• Parity error signaled on cache access
• Write bus error on buffered store or cache line push
Data storage IVOR 2 — SRR[0:1] • Access control
• Byte ordering due to misaligned access across page
boundary to pages with mismatched E bits
• Cache locking exception
• Precise external termination error
Instruction
storage IVOR 3 — SRR[0:1] • Access control.
• Precise external termination error.
External input IVOR 4
2
EE, src SRR[0:1] External interrupt is asserted and MSR[EE]=1
Alignment IVOR 5 — SRR[0:1] • lmw , stmw not word aligned
• lwarx or stwcx. not word aligned
• dcbz with disabled cache or no cache present, or to W or I
storage
• SPE ld and st instructions not properly aligned
Program IVOR 6 — SRR[0:1] Illegal, privileged, trap, FP enabled, AP enabled,
unimplemented operation
Floating-point
unavailable IVOR 7 — SRR[0:1] MSR[FP]=0 and attempt to execute a Book E floating point
operation
System call IVOR 8 — SRR[0:1] Execution of the system call ( sc ) instruction
AP unavailable IVOR 9 — SRR[0:1] Unused by e200z6
Decrementer IVOR 10 EE, DIE SRR[0:1] Decrementer timeout, and as specified in Book E: Enhanced
PowerPC
TM
Architecture, Rev 1.0 , Ch. 8, pg. 194–195 and in
the e200Z6 PowerPC
tm
Core Reference Manual, Rev 0.
Fixed interval
timer IVOR 11 EE, FIE SRR[0:1] Fixed-interval timer timeout and as specified in Book E:
Enhanced PowerPC
TM
Architecture, Rev 1.0 , Ch. 8, pg.
195–196 and in the e200Z6 PowerPC
tm
Core Reference
Manual, Rev 0.
Watchdog
timer IVOR 12 CE, WIE CSRR[0:1] Watchdog timeout: as specified in Book E: Enhanced
PowerPC
TM
Architecture, Rev 1.0 , Ch. 8, pg. 196–197 and in
the e200Z6 PowerPC
TM
Core Reference Manual, Rev 0.
Data TLB error IVOR 13 — SRR[0:1] Data translation lookup did not match a valid entry in the TLB
Instruction TLB
error IVOR 14 — SRR[0:1] Instruction translation lookup did not match a valid TLB entry
Table 3-11. Interrupts and Conditions (continued)
Interrupt Type
Interrupt
Vector Offset
Register
Enables
1
Core Register
in Which
State
Information is
Saved
Causing Conditions