Signal Description
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor
2-17
5
The 496 assembly contains the VertiCal base and includes 324 pins.
6
The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance.
Terminology is O - output, I - input, Up - weak pullup enabled, Down - weak pulldown enabled, Low - output driven low, High - output driven high. A dash
on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side of the slash denotes that there is
no weak pullup/down enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled.
7
Function after reset of GPI is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin are off.
A dash on the right side of the slash denotes that there is no weak pullup/down enabled on the pin.
8
Tie PLLCFG[2] to ground.
9
The EBI is specified and tested at 1.8–3.3 V.
10
Do not configure both the primary function in ADDR[8:11]_GPIO[4:7] and the secondary function in CS[0:3]_ADDR[8:11]_GPIO[0:3] pins to be the
address input. Only configure one set of pins for the address input.
11
When using the EBI functions, select the function in the SIU_PCR register, and then enable the EBI functions in the EBI registers for these pins. Both
the SIU and EBI configurations must match to operation correctly.
12
The function and state of this pin(s) after execution of the BAM program is determined by the BOOTCFG[0:1] pins. Refer to
for detail on the
External Bus Interface (EBI) configuration after execution of the BAM program.
13
These signals are not available on the 324 package.
14
The functions for the WE/BE[0:1]_GPIO[64:65] and WE/BE[2:3]_CAL_WE/BE[0:1]_GPIO[66:67] pins are specified in the SIU. When configured for EBI,
the write enable or byte enable operation is specified in the EBI_BR0 through EBI_BR3 registers. When configured for the calibration bus, the write
enable or byte enable operation is specified in the EBI_CAL_BR0 through EBI_CAL_BR3 registers for each chip select region.
15
The BR and BG primary signal functions are not implemented on the MPC5565 324 package, however the pin labels remain BR and BG on the BGA
map of the 496 assembly.
16
These signals are available on the Vertical assembly only.
17
MCKO is only enabled if debug mode is enabled. Debug mode can be enabled before or after exiting System Reset (RSTOUT negated).
18
MDO[0] is driven high following a power-on reset until the system clock achieves lock, at which time it is then negated. There is an internal pullup on
MDO[0].
19
The function of the MDO[11:4]_GPIO[82:75] pins is selected during a debug port reset by the EVTI pin or by selecting FPM in the NPC_PCR. When
functioning as MDO[11:4] the pad configuration specified by the SIU does not apply. Refer to 2.3.3.4 for more detail on MDO[11:4] pin operation.
20
The function and state of the FlexCAN A pins after execution of the BAM program is determined by the BOOTCFG[0:1] pins. Refer to
for
details on the FlexCAN pin configurations after the BAM executes.
21
The primary signal is not available on this device and is listed only for reference to the pin label in the BGA Map.
22
For compatibility to the MPC5554, always power V
DDEH6
and V
DDEH10
from the same power supply 3.0–5.25 V. To allow one DSPI to operate at a
different operating voltage, connect V
DDEH6
and V
DDEH10
to separate power supplies, but this configuration is not compatible with the MPC5554,
23
All analog input channels are connected to both ADC blocks. The supply designation for this pin(s) specifies only the ESD rail used.
24
Because the primary signal function designations for the analog functions AN[12] through AN[15] are internally reserved, the PA field of the
corresponding SIU_PCR registers must be set to the main primary function value of 0b011 to use analog functions AN[12] through AN[15].
25
To use the serial data strobe functions, the PA field in the SIU_PCR registers must be set to 0b00. Because SDS, SDO, SDI, and FCK
use
the GPIO
setting, a G is shown in the P/A/G column. However, these signals do not support GPIO functionality.
26
If analog features are used, tie V
DDEH9
to V
DDA1
.
27
Because other balls already are named EMIOS[14:15], the balls for these signals are named GPIO[203:204].
28
The GPIO[205] pin is a protect-for-pin for configuring an external boot for a double data rate (DDR) memory.
29
The GPIO[206:207] pins are protect-for-pins for double data rate (DDR) memory data strobes. These pins can be selected as the source for the eQADC
trigger in the eQADC Trigger Input Select Register (SIU_ETISR).
30
The Function After Reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. Ground the XTAL pin when using bypass mode.
31
When the FMPLL is configured for external reference mode, the V
DDE5
supply affects the acceptable signal levels for the external reference. Refer to
Section 11.1.4.2, “External Reference Mode
.”
32
The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[1] pin. The operating voltage for the EXTAL
function is 3.3 V; the operating voltage for the EXTCLK function is 1.62–3.6 V.
33
V
RC33
is the 3.3 V input for the voltage regulator control.
34
The V
DDA
n
and V
SSA
n
supply inputs are split into separate traces in the package substrate. Each trace is bonded to a separate pad location, which
provides isolation between the analog and digital sections within each ADC.
35
Can be tied to 5.0 V for both read operation and program / erase.
36
Tie the V
STBY
pin to V
SSA0
if the battery backed SRAM is not used.
37
Both V
DDE2
and V
DDE3
pins are labeled as V
DDE2
pins on the BGA maps. V
DDE3
can be connected internally to V
DDE2
.
38
The V
DDEH9
segment can be powered by 3.0–5.0 V for mux addresses or SSI functions, however the V
DDEH9
segment must comply with the V
DDA1
specifications (4.5–5.25 V) for analog input functions.
39
All pins with pad type F (pad_fc) are driven to the high state if their V
DDE
segment is powered before V
DD33
.
40
The pins are reserved for the clock and inverted clock outputs for the DDR memory interface.
Summary of Contents for MPC5565
Page 18: ...MPC5565 Microcontroller Reference Manual Devices Supported MPC5565 MPC5565 RM Rev 1 0 09 2007...
Page 34: ...MPC5565 Reference Manual Rev 1 0 Freescale Semiconductor 15...
Page 35: ...MPC5565 Reference Manual Rev 1 0 16 Freescale Semiconductor...
Page 553: ...Flash Memory MPC5565 Microcontroller Reference Manual Rev 1 0 13 38 Freescale Semiconductor...
Page 559: ...SRAM MPC5565 Microcontroller Reference Manual Rev 1 0 14 6 Freescale Semiconductor...
Page 973: ...Preface MPC5565 Microcontroller Reference Manual Rev 1 0 21 36 Freescale Semiconductor...
Page 1153: ...Calibration MPC5565 Microcontroller Reference Manual Rev 1 0 B 8 Freescale Semiconductor...
