Freescale Semiconductor MPC5565, Reference Manual

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Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
11-16 Freescale Semiconductor
11.3.1.2 Synthesizer Status Register (FMPLL_SYNSR)
The synthesizer status register (FMPLL_SYNSR) is a 32-bit register. Only the LOLF and LOCF flag bits
are writable in this register. Writes to bits other than the LOLF and LOCF have no effect.
20–21
DEPTH[0:1]
Controls the frequency modulation depth and enables the frequency modulation. When programmed to a
value other than 0x0, the frequency modulation is automatically enabled. The programmable frequency
deviations from the system frequency are shown below. If the depth is changed to a value other than 0x0,
the calibration sequence is reinitialized.
Note: To avoid unintentional interrupt requests, clear LOLIRQ before changing DEPTH.
22–31
EXP[0:9]
Expected difference value. Holds the expected value of the difference of the reference and the feedback
counters. Refer to
Section 11.4.3.3, “FM Calibration Routine ” to determine the value of these bits. This field
is written by the application before entering calibration mode.
Address: Base + 0x0004 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 LOLF
LOC MODE
PLL
SEL
PLL
REF
LOCKS LOCK
LOCF CALD
ONE
CAL
PASS
W w1c w1c
Reset 0 0 0 0 0 0 0 0 —
1
—
1
—
1
—
1
—
2
0 0 0
1
Reset state determined during reset configuration. (Refer to Section 11.1.4, “FMPLL Modes of Operation ,” for more
information.)
2
Reset state determined during reset.
Note: “w1c” signifies that this bit is cleared by writing a 1 to it.
Figure 11-9. Synthesizer Status Register (FMPLL_SYNSR)
Table 11-4. FMPLL_SYNCR Field Descriptions (continued)
Field Description
DEPTH[1] DEPTH[0] Modulation Depth (% of Fsys)
0 0 0
0 1 1.0
±
0.2
1 0 2.0
±
0.2
1 1 Reserved