Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
19-58 Freescale Semiconductor
19.4.7.3 Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 0)
In this modified transfer format both the master and the slave sample later in the SCK period than in classic
SPI mode to allow for delays in device pads and board traces. These delays become a more significant
fraction of the SCK period as the SCK period decreases with increasing baud rates.
NOTE
For the modified transfer format to operate correctly, you must thoroughly
analyze the SPI link timing budget.
The master and the slave place data on the SOUT x pins at the assertion of the PCS x signal. After the PCS x
to SCK x delay has elapsed the first SCK x edge is generated. The slave samples the master SOUT x signal
on every odd numbered SCK x edge. The slave also places new data on the slave SOUT x on every odd
numbered clock edge.
The master places its second data bit on the SOUT x line one system clock after odd numbered SCK x edge.
The point where the master samples the slave SOUT x is selected by writing to the SMPL_PT field in the
DSPI x _MCR. Table 19-28 lists the number of system clock cycles between the active edge of SCK x and
the master sample point for different values of the SMPL_PT bit field. The master sample point can be
delayed by one or two system clock cycles.
Table 19-28. Delayed Master Sample Point
SMPL_PT
Number of System Clock Cycles between
Odd-numbered Edge of SCK and Sampling of SIN
00 0
01 1
10 2
11 Invalid value