Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 19-57
19.4.7.2 Classic SPI Transfer Format (CPHA = 1)
This transfer format shown in Figure 19-33 is used to communicate with peripheral SPI slave devices that
require the first SCK x edge before the first data bit becomes available on the slave SOUT pin. In this
format the master and slave devices change the data on their SOUT x pins on the odd-numbered SCK x
edges and sample the data on their SIN x pins on the even-numbered SCK x edges.
Figure 19-33. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 1, FMSZ = 8)
The master initiates the transfer by asserting the PCS x signal to the slave. After the
t
CSC
delay has elapsed,
the master generates the first SCK x edge and at the same time places valid data on the master SOUT x pin.
The slave responds to the first SCK x edge by placing its first data bit on its slave SOUT x pin.
At the second edge of the SCK x the master and slave sample their SIN x pins. For the rest of the frame the
master and the slave change the data on their SOUT x pins on the odd-numbered clock edges and sample
their SIN x pins on the even-numbered clock edges. After the last clock edge occurs a delay of t
ASC
is
inserted before the master negates the PCS x signal. A delay of t
DT
is inserted before a new frame transfer
can be initiated by the master.
For CPHA = 1 the master EOQF and TCF and slave TCF are set at the last serial clock edge (edge 16) of
Figure 19-33 . For CPHA = 1 the master and slave RXCTR counters are updated on the same clock edge.
Slave (CPHA = 1): TCF is set and RXCTR counter is updated at
last SCK edge of frame (edge 16)
SCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
(CPOL = 0)
PCSx / SS
t
ASC
SCK
(CPOL = 1)
Master and slave
sample
Master SOUT/
Slave SIN
Master SIN/
Slave SOUT
Bit 6
Bit 1 Bit 5
Bit 2 Bit 4
Bit 3 Bit 3
Bit 4 Bit 2
Bit 5 Bit 1
Bit 6 LSB
MSB
MSB
LSB
t
DT
t
CSC
MSB first (LSBFE = 0):
LSB first (LSBFE = 1):
t
CSC
= PCS to SCK delay.
t
ASC
= After SCK delay.
t
DT
= Delay after transfer (minimum CS negation time).
Master (CPHA = 1): TCF and EOQF are set and RXCTR counter
is updated at last SCK edge of frame (edge 16)
16