Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
18-20 Freescale Semiconductor
18.3.2.7 eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCR n )
The eQADC_IDCRs contain bits to enable the generation of interrupt or eDMA requests when the
corresponding flag bits are set in EQADC_FISRn. Refer to
Section 18.3.2.8, “eQADC FIFO and Interrupt
Status Registers 0–5 (EQADC_FISRn) .”
0b0100 Falling edge external trigger, single scan
0b0101 Rising edge external trigger, single scan
0b0110 Falling or rising edge external trigger, single scan
0b0111–0b1000 Reserved
0b1001 Software trigger, continuous scan
0b1010 Low level gated external trigger, continuous scan
0b1011 High level gated external trigger, continuous scan
0b1100 Falling edge external trigger, continuous scan
0b1101 Rising edge external trigger, continuous scan
0b1110 Falling or rising edge external trigger, continuous scan
0b1111 Reserved
Address: EQAD 0x060 (EQADC_IDCR0)
EQAD 0x062 (EQADC_IDCR1)
EQAD 0x064 (EQADC_IDCR2)
EQAD 0x066 (EQADC_IDCR3)
EQAD 0x068 (EQADC_IDCR4)
EQAD 0x06A (EQADC_IDCR5) Access: Read/Write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
NCI
E n
TORI
E n
PIE n
EOQI
E n
CFUI
E n
0
CFF
E n
CFF
S n
0 0 0 0
RFOI
E n
0
RFD
E n
RFD
S n
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-8. eQADC Interrupt and eDMA Control Registers 0–5 (EQADC_IDCR n )
Table 18-10. CFIFO Operation Mode Table (continued)
MODE n [0:3] CFIFO Operation Mode