Freescale Semiconductor MPC5565, Reference Manual

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External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 12-23
12.4.1.6 Burst Support (Wrapped Only)
The EBI supports burst read accesses of external burstable memory. To enable bursts to a particular
memory region, clear the BI (Burst Inhibit) bit in the appropriate base register. External burst lengths of 4
and 8 words are supported. Burst length is configured for each chip select by using the BL bit in the
appropriate base register. Refer to
Section 12.4.2.5, “Burst Transfer ” for more details.
In 16-bit data bus mode (EBI_MCR[DBM] = 1), a special 2-beat burst case is supported for reads and
writes for 32-bit non-chip select accesses only. This is to allow 32-bit coherent accesses to another MCU.
Refer to
Section 12.4.2.11, “Non-Chip-Select Burst in 16-bit Data Bus Mode .”
Bursting of accesses that are not controlled by the chip selects is not supported for any other case besides
the special case of 32-bit accesses in 16-bit data bus mode.
Burst writes are not supported for any other case besides the special case of 32-bit non-chip select writes
in 16-bit data bus mode. Internal requests to write more than 32 bits (such as a cache line) externally are
broken up into separate 32-bit or 16-bit external transactions according to the port size. Refer to
Section 12.4.2.6, “Small Accesses (Small Port Size and Short Burst Length) ” for more detail on these
cases.
12.4.1.7 Bus Monitor
When enabled (via the BME bit in the EBI_BMCR), the bus monitor detects when no TA assertion is
received within a maximum timeout period for non-chip select accesses (that is, accesses that use external
TA). The timeout for the bus monitor is specified by the BMT field in the EBI_BMCR. Each time a timeout
error occurs, the BMTF bit is set in the EBI_TESR. The timeout period is measured in external bus
(CLKOUT) cycles. Thus the effective real-time period is multiplied (by two or four) when a configurable
bus speed mode is used, even though the BMT field itself is unchanged.
12.4.1.8 Port Size Configuration per Chip Select (16 or 32 Bits)
The EBI supports memories with data widths of 16 or 32 bits. The port size (PS) for a chip select is
configured using the PS bit in the base register.
Table 12-12. Default Attributes for Transfers Other than Chip Select
CS Attribute Default Value Comment
PS 0 32-bit port size
BL 0 Burst is disabled – length is variable
WEBS 0 Write enables
TBDIP 0 Burst is disabled – length variable
BI 1 Burst inhibited
SCY 0 Transfer acknowledge (TA) used – length variable
BSCY 0 Transfer acknowledge (TA) used – length variable