Freescale Semiconductor MPC5565, Reference Manual

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External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
12-58 Freescale Semiconductor
Figure 12-39. Single-Beat CS Read Cycle in External Master Mode, Zero Wait States
12.4.2.11 Non-Chip-Select Burst in 16-bit Data Bus Mode
The timing diagrams in this section apply only to the special case of a non-chip select 32-bit access in
16-bit data bus mode. They specify the behavior for both the EBI-master and EBI-slave, as the external
master is expected to be another MCU with this EBI.
For this case, a special two-beat burst protocol is used for reads and writes, so that the EBI-slave can
internally generate one 32-bit read or write access (thus 32-bit coherent), as opposed to two separate 16-bit
accesses.
Figure 12-40 shows a 32-bit read from an external master in 16-bit data bus mode.
Figure 12-41 shows a 32-bit write from an external master in 16-bit data bus mode.
CLKOUT
RD_WR
BDIP
ADDR[8:31]
DATA[0:31]
1
TS
TA
CS [ n ]
OE
DATA is valid
1
The 324 package only has DATA[0:15] for this device.