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6
SLAU723A – October 2017 – Revised October 2018
Copyright © 2017–2018, Texas Instruments Incorporated
Contents
4.2.98
RCGCACMP Register (Offset = 0x63C) [reset = 0x0]
.....................................................
4.2.99
RCGCPWM Register (Offset = 0x640) [reset = 0x0]
.......................................................
4.2.100
RCGCQEI Register (Offset = 0x644) [reset = 0x0]
.......................................................
4.2.101
RCGCEEPROM Register (Offset = 0x658) [reset = 0x0]
................................................
4.2.102
RCGCCCM Register (Offset = 0x674) [reset = 0x0]
......................................................
4.2.103
RCGCLCD Register (Offset = 0x690) [reset = 0x0]
......................................................
4.2.104
RCGCOWIRE Register (Offset = 0x698) [reset = 0x0]
...................................................
4.2.105
RCGCEMAC Register (Offset = 0x69C) [reset = 0x0]
...................................................
4.2.106
SCGCWD Register (Offset = 0x700) [reset = 0x0]
.......................................................
4.2.107
SCGCTIMER Register (Offset = 0x704) [reset = 0x00]
..................................................
4.2.108
SCGCGPIO Register (Offset = 0x708) [reset = 0x00]
....................................................
4.2.109
SCGCDMA Register (Offset = 0x70C) [reset = 0x0]
.....................................................
4.2.110
SCGCEPI Register (Offset = 0x710) [reset = 0x0]
.......................................................
4.2.111
SCGCHIB Register (Offset = 0x714) [reset = 0x1]
.......................................................
4.2.112
SCGCUART Register (Offset = 0x718) [reset = 0x00]
...................................................
4.2.113
SCGCSSI Register (Offset = 0x71C) [reset = 0x0]
.......................................................
4.2.114
SCGCI2C Register (Offset = 0x720) [reset = 0x00]
......................................................
4.2.115
SCGCUSB Register (Offset = 0x728) [reset = 0x0]
......................................................
4.2.116
SCGCEPHY Register (Offset = 0x730) [reset = 0x0]
.....................................................
4.2.117
SCGCCAN Register (Offset = 0x734) [reset = 0x0]
......................................................
4.2.118
SCGCADC Register (Offset = 0x738) [reset = 0x0]
......................................................
4.2.119
SCGCACMP Register (Offset = 0x73C) [reset = 0x0]
....................................................
4.2.120
SCGCPWM Register (Offset = 0x740) [reset = 0x0]
.....................................................
4.2.121
SCGCQEI Register (Offset = 0x744) [reset = 0x0]
.......................................................
4.2.122
SCGCEEPROM Register (Offset = 0x758) [reset = 0x0]
................................................
4.2.123
SCGCCCM Register (Offset = 0x774) [reset = 0x0]
......................................................
4.2.124
SCGCLCD Register (Offset = 0x790) [reset = 0x0]
......................................................
4.2.125
SCGCOWIRE Register (Offset = 0x798) [reset = 0x0]
...................................................
4.2.126
SCGCEMAC Register (Offset = 0x79C) [reset = 0x0]
....................................................
4.2.127
DCGCWD Register (Offset = 0x800) [reset = 0x0]
.......................................................
4.2.128
DCGCTIMER Register (Offset = 0x804) [reset = 0x00]
..................................................
4.2.129
DCGCGPIO Register (Offset = 0x808) [reset = 0x00]
...................................................
4.2.130
DCGCDMA Register (Offset = 0x80C) [reset = 0x0]
.....................................................
4.2.131
DCGCEPI Register (Offset = 0x810) [reset = 0x0]
.......................................................
4.2.132
DCGCHIB Register (Offset = 0x814) [reset = 0x1]
.......................................................
4.2.133
DCGCUART Register (Offset = 0x818) [reset = 0x00]
...................................................
4.2.134
DCGCSSI Register (Offset = 0x81C) [reset = 0x0]
.......................................................
4.2.135
DCGCI2C Register (Offset = 0x820) [reset = 0x00]
......................................................
4.2.136
DCGCUSB Register (Offset = 0x828) [reset = 0x0]
......................................................
4.2.137
DCGCEPHY Register (Offset = 0x830) [reset = 0x0]
....................................................
4.2.138
DCGCCAN Register (Offset = 0x834) [reset = 0x0]
......................................................
4.2.139
DCGCADC Register (Offset = 0x838) [reset = 0x0]
......................................................
4.2.140
DCGCACMP Register (Offset = 0x83C) [reset = 0x0]
...................................................
4.2.141
DCGCPWM Register (Offset = 0x840) [reset = 0x0]
.....................................................
4.2.142
DCGCQEI Register (Offset = 0x844) [reset = 0x0]
.......................................................
4.2.143
DCGCEEPROM Register (Offset = 0x858) [reset = 0x0]
................................................
4.2.144
DCGCCCM Register (Offset = 0x874) [reset = 0x0]
......................................................
4.2.145
DCGCLCD Register (Offset = 0x890) [reset = 0x0]
......................................................
4.2.146
DCGCOWIRE Register (Offset = 0x898) [reset = 0x0]
...................................................
4.2.147
DCGCEMAC Register (Offset = 0x89C) [reset = 0x0]
...................................................
4.2.148
PCWD Register (Offset = 0x900) [reset = 0x3]
...........................................................
4.2.149
PCTIMER Register (Offset = 0x904) [reset = 0xFF]
......................................................
4.2.150
PCGPIO Register (Offset = 0x908) [reset = 0x3FFFF]
...................................................