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Initialization and Configuration
1096
SLAU723A – October 2017 – Revised October 2018
Copyright © 2017–2018, Texas Instruments Incorporated
External Peripheral Interface (EPI)
the CSn modes can be enhanced to access four external devices using settings in the EPIHBnCFGn
register. PSRAM accesses must use both ALE and CSn. Wait states can be added to the data phase of
the access using the WRWS and RDWS bits in the EPIHBnCFGn register. Additionally, within these wait
state options, the WRWSM and RDWSM bit of the EPIHBnTIMEn register can be set to reduce the given
wait states by 1 EPI clock cycle for finer granularity.
For FIFO mode, the ALE is not used, and two input holds are optionally supported to gate input and output
to what the XFIFO can handle. FIFO mode is only applicable in EPI asynchronous mode.
Host-bus 8 and host-bus 16 modes are very configurable. The user has the ability to connect 1, 2, or 4
external devices to the EPI signals, as well as control whether byte select signals are provided in HB16
mode. These capabilities depend on the configuration of the MODE field in the EPIHBnCFG register, the
CSCFG field and the CSCFGEXT bit in the EPIHBnCFGn register, and the BSEL bit in the EPIHB16CFG
register. The CSCFGEXT bit extends the chip select configuration possibilities by providing the most
significant bit of the CSCFGEXT field. For the possible ALE and chip select options that can be
programmed by the combination of the CSCFGEXT and CSCFGEXT bits, see
. CSCFGEXT is
the most significant bit.
Table 16-3. CSCFGEXT and CSCFG Encodings
Value
Description
0x0
ALE configuration
EPI0S30 is used as an address latch (ALE). The ALE signal is generally used when the address and data are
muxed (MODE field in the EPIHB8CFG register is 0x0). The ALE signal is used by an external latch to hold the
address through the bus cycle.
0x1
CSn Configuration
EPI0S30 is used as a chip select (CSn). When using this mode, the address and data are generally not muxed
(MODE field in the EPIHB8CFG register is 0x1). However, if address and data muxing is needed, the WR signal
(EPI0S29) and the RD signal (EPI0S28) can be used to latch the address when CSn is low.
0x2
Dual CSn configuration
EPI0S30 is used as CS0n and EPI0S27 is used as CS1n. Whether CS0n or CS1n is asserted is determined by
the most significant address bit for a respective external address map. This configuration can be used for a RAM
bank split between 2 devices and when using both an external RAM and an external peripheral.
0x3
ALE with dual CSn configuration
EPI0S30 is used as address latch (ALE), EPI0S27 is used as CS1n, and EPI0S26 is used as CS0n. Whether
CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address
map.
0x4
ALE with single CSn configuration
EPI0S30 is used as address latch (ALE) and EPI0S27 is used as CSn.
0x5
Quad CSn configuration
EPI0S30 is used as CS0n, EPI0S27 is used as CS1n, EPI0S34 is used as CS2n, and EPI0S33 is used as CS3n.
0x6
ALE with quad CSn configuration
EPI0S30 is used as ALE, EPI0S26 is used as CS0n, EPI0S27 is used as CS1n, EPI0S34 is used as CS2n,and
EPI0S33 is used as CS3n.
0x7
Reserved
If one of the dual-chip-select modes is selected (CSCFGEXT is 0x0 and CSCFG is 0x2 or 0x3 in the
EPIHBnCFGn register), both chip selects can share the peripheral, code, or the memory space, or one
chip select can use the peripheral space and the other can use the memory or code space. In the
EPIADDRMAP register, if the EPADR field is not 0x0, the ECADR field is 0x0, and the ERADR field is
0x0, then the address specified by EPADR is used for both chip selects, with CS0n being asserted when
the MSB of the address range is 0 and CS1n being asserted when the MSB of the address range is 1. If
the ERADR field is not 0x0, the ECADR field is 0x0, and the EPADR field is 0x0, then the address
specified by ERADR is used for both chip selects, with the MSB performing the same delineation. If both
the EPADR and the ERADR are not 0x0, and the ECADR field is 0x0 and the EPI is configured for dual-
chip selects, then CS0n is asserted for either address range defined by EPADR and CS1n is asserted for
either address range defined by ERADR. The two chip selects can also be shared between the code
space and memory or peripheral space. If the ECADR field is 0x1, ERADR field is 0x0, and the EPADR
field is not 0x0, then CS0n is asserted for the address range defined by ECADR and CS1n is asserted for
either address range defined by EPADR. If the ECADR field is 0x1, EPADR field is 0x0, and the ERADR
field is not 0x0, then CS0n is asserted for the address range defined by ECADR and CS1n is asserted for
either address range defined by ERADR.