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GPIO Registers
1231
SLAU723A – October 2017 – Revised October 2018
Copyright © 2017–2018, Texas Instruments Incorporated
General-Purpose Input/Outputs (GPIOs)
17.5.23 GPIOADCCTL Register (Offset = 0x530) [reset = 0x0]
GPIO ADC Control (GPIOADCCTL)
This register is used to configure a GPIO pin as a source for the ADC trigger.
Note that if the Port B GPIOADCCTL register is cleared, PB4 can still be used as an external trigger for
the ADC. This is a legacy mode which allows code written for previous devices to operate on this
microcontroller.
GPIOADCCTL is shown in
and described in
Return to
Figure 17-27. GPIOADCCTL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
ADCEN
R-0x0
R/W-0x0
Table 17-34. GPIOADCCTL Register Field Descriptions
Bit
Field
Type
Reset
Description
31-8
RESERVED
R
0x0
7-0
ADCEN
R/W
0x0
ADC Trigger Enable.
0x0 = The corresponding pin is not used to trigger the ADC.
0x1 = The corresponding pin is used to trigger the ADC.