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CAN Registers
803
SLAU723A – October 2017 – Revised October 2018
Copyright © 2017–2018, Texas Instruments Incorporated
Controller Area Network (CAN) Module
11.4 CAN Registers
lists the memory-mapped registers for the CAN. All register offset addresses not listed in
should be considered as RESERVED locations and the register contents should not be
modified.
All address offsets are relative to the base address of the CAN module:
•
CAN0: 0x40040000
•
CAN1: 0x40041000
The CAN controller clock must be enabled before the registers can be programmed. There must be a
delay of 3 system clock cycles after the CAN module clock is enabled before any CAN module registers
are accessed.
Table 11-6. CAN Registers
Offset
Acronym
Register Name
Section
0x0
CANCTL
CAN Control
0x4
CANSTS
CAN Status
0x8
CANERR
CAN Error Counter
0xC
CANBIT
CAN Bit Timing
0x10
CANINT
CAN Interrupt
0x14
CANTST
CAN Test
0x18
CANBRPE
CAN Baud Rate Prescaler Extension
0x20
CANIF1CRQ
CAN IF1 Command Request
0x24
CANIF1CMSK
CAN IF1 Command Mask
0x28
CANIF1MSK1
CAN IF1 Mask 1
0x2C
CANIF1MSK2
CAN IF1 Mask 2
0x30
CANIF1ARB1
CAN IF1 Arbitration 1
0x34
CANIF1ARB2
CAN IF1 Arbitration 2
0x38
CANIF1MCTL
CAN IF1 Message Control
0x3C
CANIF1DA1
CAN IF1 Data A1
0x40
CANIF1DA2
CAN IF1 Data A2
0x44
CANIF1DB1
CAN IF1 Data B1
0x48
CANIF1DB2
CAN IF1 Data B2
0x80
CANIF2CRQ
CAN IF2 Command Request
0x84
CANIF2CMSK
CAN IF2 Command Mask
0x88
CANIF2MSK1
CAN IF2 Mask 1
0x8C
CANIF2MSK2
CAN IF2 Mask 2
0x90
CANIF2ARB1
CAN IF2 Arbitration 1
0x94
CANIF2ARB2
CAN IF2 Arbitration 2
0x98
CANIF2MCTL
CAN IF2 Message Control
0x9C
CANIF2DA1
CAN IF2 Data A1
0xA0
CANIF2DA2
CAN IF2 Data A2
0xA4
CANIF2DB1
CAN IF2 Data B1
0xA8
CANIF2DB2
CAN IF2 Data B2
0x100
CANTXRQ1
CAN Transmission Request 1
0x104
CANTXRQ2
CAN Transmission Request 2
0x120
CANNWDA1
CAN New Data 1
0x124
CANNWDA2
CAN New Data 2
0x140
CANMSG1INT
CAN Message 1 Interrupt Pending
0x144
CANMSG2INT
CAN Message 2 Interrupt Pending
0x160
CANMSG1VAL
CAN Message 1 Valid